diff options
author | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-06 20:33:39 +0200 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-12 04:24:29 +0200 |
commit | 10284bfa347815fcce3f7133860fb9570576f8ab (patch) | |
tree | 5bde4cf8707873ff36d9d9739f337cb7de2159ae /drivers/pci/host | |
parent | PCI: exynos: Uninline register accessors (diff) | |
download | linux-10284bfa347815fcce3f7133860fb9570576f8ab.tar.xz linux-10284bfa347815fcce3f7133860fb9570576f8ab.zip |
PCI: exynos: Name private struct pointer "exynos_pcie" consistently
Most struct exynos_pcie pointers are already called "exynos_pcie". Change
the rest of them to match. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/host')
-rw-r--r-- | drivers/pci/host/pci-exynos.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index 8e841f8340d5..2b4d88633040 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -102,34 +102,34 @@ struct exynos_pcie { #define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7) #define PCIE_PHY_TRSV3_LVCC 0x31c -static void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg) +static void exynos_elb_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg) { - writel(val, pcie->elbi_base + reg); + writel(val, exynos_pcie->elbi_base + reg); } -static u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg) +static u32 exynos_elb_readl(struct exynos_pcie *exynos_pcie, u32 reg) { - return readl(pcie->elbi_base + reg); + return readl(exynos_pcie->elbi_base + reg); } -static void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg) +static void exynos_phy_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg) { - writel(val, pcie->phy_base + reg); + writel(val, exynos_pcie->phy_base + reg); } -static u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg) +static u32 exynos_phy_readl(struct exynos_pcie *exynos_pcie, u32 reg) { - return readl(pcie->phy_base + reg); + return readl(exynos_pcie->phy_base + reg); } -static void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg) +static void exynos_blk_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg) { - writel(val, pcie->block_base + reg); + writel(val, exynos_pcie->block_base + reg); } -static u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg) +static u32 exynos_blk_readl(struct exynos_pcie *exynos_pcie, u32 reg) { - return readl(pcie->block_base + reg); + return readl(exynos_pcie->block_base + reg); } static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on) |