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authorTal Gilboa <talgi@mellanox.com>2018-03-30 15:32:03 +0200
committerBjorn Helgaas <bhelgaas@google.com>2018-03-30 22:33:38 +0200
commitb852f63aa6cee3f4846383377c414ae9c4fbc166 (patch)
tree55fd810d9b5c8b029cf63bc4e70ee4990275b66a /drivers/pci/pci.h
parentPCI: Add pcie_get_width_cap() to find max supported link width (diff)
downloadlinux-b852f63aa6cee3f4846383377c414ae9c4fbc166.tar.xz
linux-b852f63aa6cee3f4846383377c414ae9c4fbc166.zip
PCI: Add pcie_bandwidth_capable() to compute max supported link bandwidth
Add pcie_bandwidth_capable() to compute the max link bandwidth supported by a device, based on the max link speed and width, adjusted by the encoding overhead. The maximum bandwidth of the link is computed as: max_link_width * max_link_speed * (1 - encoding_overhead) 2.5 and 5.0 GT/s links use 8b/10b encoding, which reduces the raw bandwidth available by 20%; 8.0 GT/s and faster links use 128b/130b encoding, which reduces it by about 1.5%. The result is in Mb/s, i.e., megabits/second, of raw bandwidth. Signed-off-by: Tal Gilboa <talgi@mellanox.com> [bhelgaas: add 16 GT/s, adjust for pcie_get_speed_cap() and pcie_get_width_cap() signatures, don't export outside drivers/pci] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/pci.h')
-rw-r--r--drivers/pci/pci.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 66738f1050c0..ce9adec6c66e 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -261,8 +261,18 @@ void pci_disable_bridge_window(struct pci_dev *dev);
(speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
"Unknown speed")
+/* PCIe speed to Mb/s reduced by encoding overhead */
+#define PCIE_SPEED2MBS_ENC(speed) \
+ ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
+ (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
+ (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
+ (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
+ 0)
+
enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
+u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
+ enum pcie_link_width *width);
/* Single Root I/O Virtualization */
struct pci_sriov {