summaryrefslogtreecommitdiffstats
path: root/drivers/pci/pci.h
diff options
context:
space:
mode:
authorVidya Sagar <vidyas@nvidia.com>2020-10-24 21:04:42 +0200
committerBjorn Helgaas <bhelgaas@google.com>2020-11-20 18:17:44 +0100
commit4257f7e008ea394fcecc050f1569c3503b8bcc15 (patch)
tree08477e23d2d204d8f7b9081f3df3df1e2760891e /drivers/pci/pci.h
parentLinux 5.10-rc3 (diff)
downloadlinux-4257f7e008ea394fcecc050f1569c3503b8bcc15.tar.xz
linux-4257f7e008ea394fcecc050f1569c3503b8bcc15.zip
PCI/ASPM: Save/restore L1SS Capability for suspend/resume
Previously ASPM L1 Substates control registers (CTL1 and CTL2) weren't saved and restored during suspend/resume leading to L1 Substates configuration being lost post-resume. Save the L1 Substates control registers so that the configuration is retained post-resume. Link: https://lore.kernel.org/r/20201024190442.871-1-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/pci.h')
-rw-r--r--drivers/pci/pci.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index f86cae9aa1f4..60308cd1cffc 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -564,11 +564,15 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev);
void pcie_aspm_exit_link_state(struct pci_dev *pdev);
void pcie_aspm_pm_state_change(struct pci_dev *pdev);
void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
+void pci_save_aspm_l1ss_state(struct pci_dev *dev);
+void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
#else
static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
+static inline void pci_save_aspm_l1ss_state(struct pci_dev *dev) { }
+static inline void pci_restore_aspm_l1ss_state(struct pci_dev *dev) { }
#endif
#ifdef CONFIG_PCIE_ECRC