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author | Bjorn Helgaas <bhelgaas@google.com> | 2024-07-19 17:10:32 +0200 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2024-07-19 17:10:32 +0200 |
commit | 8240a9b4a5a27ce20a0ae2dea2b2e830be34f3b9 (patch) | |
tree | 2e38c765162174053f62e53c9c5aba39be031960 /drivers/pci/pci.h | |
parent | Merge branch 'pci/controller/rcar-gen4' (diff) | |
parent | PCI: dw-rockchip: Use pci_epc_init_notify() directly (diff) | |
download | linux-8240a9b4a5a27ce20a0ae2dea2b2e830be34f3b9.tar.xz linux-8240a9b4a5a27ce20a0ae2dea2b2e830be34f3b9.zip |
Merge branch 'pci/controller/rockchip'
- Use dev_err_probe() in dw-rockchip probe error path so the failures
aren't silent (Uwe Kleine-König)
- Sleep PCIE_T_PVPERL_MS (100ms) before deasserting PERST# (Damien Le Moal)
- Sleep PCIE_T_RRS_READY_MS (100ms) after conventional reset, before a
config access (Damien Le Moal)
- Request the PERST# GPIO with GPIOD_OUT_LOW so it matches the POR value,
which avoids a spurious PERST# assertion and fixes a Qcom modem firmware
crash and issues with WLAN controllers, e.g., RTL8822CE (Manivannan
Sadhasivam for rockchip, Niklas Cassel for dw-rockchip)
- Refactor dw-rockchip and add support for Endpoint mode for rk3568 and
rk3588 (Niklas Cassel)
* pci/controller/rockchip:
PCI: dw-rockchip: Use pci_epc_init_notify() directly
PCI: dw-rockchip: Add endpoint mode support
PCI: dw-rockchip: Refactor the driver to prepare for EP mode
PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper
PCI: dw-rockchip: Fix weird indentation
PCI: dw-rockchip: Fix initial PERST# GPIO value
PCI: dw-rockchip: Add error messages in .probe() error paths
PCI: rockchip: Use GPIOD_OUT_LOW flag while requesting ep_gpio
PCI: rockchip-host: Wait 100ms after reset before starting configuration
PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handling
Diffstat (limited to 'drivers/pci/pci.h')
-rw-r--r-- | drivers/pci/pci.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 49a705bef180..79c8398f3938 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -17,6 +17,13 @@ #define PCIE_T_PVPERL_MS 100 /* + * End of conventional reset (PERST# de-asserted) to first configuration + * request (device able to respond with a "Request Retry Status" completion), + * from PCIe r6.0, sec 6.6.1. + */ +#define PCIE_T_RRS_READY_MS 100 + +/* * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> * Recommends 1ms to 10ms timeout to check L2 ready. */ |