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authorBjorn Helgaas <bhelgaas@google.com>2020-12-15 22:11:08 +0100
committerBjorn Helgaas <bhelgaas@google.com>2020-12-15 22:11:08 +0100
commit6db645f99cc5357ab5520982b85396487c113dc9 (patch)
tree0431721fd4cc7b3814371aa734c0b6cfa439be36 /drivers/pci/probe.c
parentMerge branch 'pci/hotplug' (diff)
parentPCI: Reduce pci_set_cacheline_size() message to debug level (diff)
downloadlinux-6db645f99cc5357ab5520982b85396487c113dc9.tar.xz
linux-6db645f99cc5357ab5520982b85396487c113dc9.zip
Merge branch 'pci/misc'
- Update kernel-doc to match function prototypes (Mauro Carvalho Chehab) - Bounds-check "pci=resource_alignment=" requests (Bjorn Helgaas) - Fix integer overflow in "pci=resource_alignment=" requests (Colin Ian King) - Remove unused HAVE_PCI_SET_MWI definition (Heiner Kallweit) - Reduce pci_set_cacheline_size() message to debug level (Heiner Kallweit) * pci/misc: PCI: Reduce pci_set_cacheline_size() message to debug level PCI: Remove unused HAVE_PCI_SET_MWI PCI: Fix overflow in command-line resource alignment requests PCI: Bounds-check command-line resource alignment requests PCI: Fix kernel-doc markup # Conflicts: # drivers/pci/pci-driver.c
Diffstat (limited to 'drivers/pci/probe.c')
-rw-r--r--drivers/pci/probe.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index e4fe6a740d1d..951b748bacbd 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -165,7 +165,7 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
/**
- * pci_read_base - Read a PCI BAR
+ * __pci_read_base - Read a PCI BAR
* @dev: the PCI device
* @type: type of the BAR
* @res: resource buffer to be filled in
@@ -1613,7 +1613,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
}
/**
- * pci_cfg_space_size - Get the configuration space size of the PCI device
+ * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
* @dev: PCI device
*
* Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices