diff options
| author | Thinh Nguyen <thinh.nguyen@synopsys.com> | 2019-02-07 00:17:27 +0100 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2019-02-07 00:17:27 +0100 |
| commit | f57a98e1b71357713e44c57268a53d9c803f0626 (patch) | |
| tree | 14f4ba4d28ce4f9904ddbbdb3332537c24474b2d /drivers/pci/quirks.c | |
| parent | Revert "PCI: armada8k: Add support for gpio controlled reset signal" (diff) | |
| download | linux-f57a98e1b71357713e44c57268a53d9c803f0626.tar.xz linux-f57a98e1b71357713e44c57268a53d9c803f0626.zip | |
PCI: Work around Synopsys duplicate Device ID (HAPS USB3, NXP i.MX)
There are at least four different parts with the same Vendor and Device
ID ([16c3:abcd]):
1) Synopsys HAPS USB3 controller
2) Synopsys PCIe Root Port in Freescale/NXP i.MX6Q (reported by Lucas)
3) Synopsys PCIe Root Port in Freescale/NXP i.MX6QP (reported by Lukas)
4) Synopsys PCIe Root Port in Freescale/NXP i.MX7D (reported by Trent)
The HAPS USB3 controller has a Class Code of PCI_CLASS_SERIAL_USB_XHCI,
which means the XHCI driver would normally claim it. Previously,
quirk_synopsys_haps() changed the Class Code of all [16c3:abcd] devices,
including the Root Ports, to PCI_CLASS_SERIAL_USB_DEVICE to prevent the
XHCI driver from claiming them so dwc3-haps can claim them instead.
Changing the Class Code of the Root Ports prevents the PCI core from
handling them as bridges, so devices below them don't work.
Restrict the quirk so it only changes the Class Code for devices that start
with the PCI_CLASS_SERIAL_USB_XHCI Class Code, leaving the Root Ports
alone.
Fixes: 03e6742584af ("PCI: Override Synopsys USB 3.x HAPS device class")
Reported-by: Lukas F. Hartmann <lukas@mntmn.com>
Reported-by: Trent Piepho <tpiepho@impinj.com>
Reported-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/pci/quirks.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index b0a413f3f7ca..e2a879e93d86 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -639,8 +639,9 @@ static void quirk_synopsys_haps(struct pci_dev *pdev) break; } } -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, - quirk_synopsys_haps); +DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, + PCI_CLASS_SERIAL_USB_XHCI, 0, + quirk_synopsys_haps); /* * Let's make the southbridge information explicit instead of having to |