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| author | Alex Williamson <alex.williamson@redhat.com> | 2017-01-19 16:51:30 +0100 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-01-28 21:46:02 +0100 |
| commit | 7184f5b451cf3dc61de79091d235b5d2bba2782d (patch) | |
| tree | 4d561b92857246fb58dd73bea5d983d0448c0b21 /drivers/pci/quirks.c | |
| parent | Linux 4.10-rc1 (diff) | |
| download | linux-7184f5b451cf3dc61de79091d235b5d2bba2782d.tar.xz linux-7184f5b451cf3dc61de79091d235b5d2bba2782d.zip | |
PCI: Add ACS quirk for Intel Union Point
Intel 200-series chipsets have the same errata as 100-series: the ACS
capability doesn't follow the PCIe spec, the capability and control
registers are dwords rather than words. Add PCIe root port device IDs to
existing quirk.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/quirks.c')
| -rw-r--r-- | drivers/pci/quirks.c | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 1800befa8b8b..a0b3cd5726dc 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4150,15 +4150,35 @@ static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) * * N.B. This doesn't fix what lspci shows. * + * The 100 series chipset specification update includes this as errata #23[3]. + * + * The 200 series chipset (Union Point) has the same bug according to the + * specification update (Intel 200 Series Chipset Family Platform Controller + * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, + * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this + * chipset include: + * + * 0xa290-0xa29f PCI Express Root port #{0-16} + * 0xa2e7-0xa2ee PCI Express Root port #{17-24} + * * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html + * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html + * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html + * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html */ static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) { - return pci_is_pcie(dev) && - pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT && - ((dev->device & ~0xf) == 0xa110 || - (dev->device >= 0xa167 && dev->device <= 0xa16a)); + if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) + return false; + + switch (dev->device) { + case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ + case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ + return true; + } + + return false; } #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) |