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| author | Niklas Cassel <niklas.cassel@axis.com> | 2018-03-28 13:50:12 +0200 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2018-04-03 13:38:04 +0200 |
| commit | a2ea8ac4ec72da44e2cf508e6431db0487b26893 (patch) | |
| tree | 1e594348bb59e89e7a4ffc4b0b786861e246c46f /drivers/pci | |
| parent | PCI: designware-ep: Make dw_pcie_ep_set_bar() handle 64-bit BARs properly (diff) | |
| download | linux-a2ea8ac4ec72da44e2cf508e6431db0487b26893.tar.xz linux-a2ea8ac4ec72da44e2cf508e6431db0487b26893.zip | |
PCI: cadence: Set PCI_BASE_ADDRESS_MEM_TYPE_64 if a 64-bit BAR was set-up
cdns_pcie_ep_set_bar() does some round-up of the BAR size, which means
that a 64-bit BAR can be set-up, even when the flag
PCI_BASE_ADDRESS_MEM_TYPE_64 isn't set.
If a 64-bit BAR was set-up, set the flag PCI_BASE_ADDRESS_MEM_TYPE_64,
so that the calling function can know what BAR width that was actually
set-up.
I'm not sure why cdns_pcie_ep_set_bar() doesn't obey the flag
PCI_BASE_ADDRESS_MEM_TYPE_64, but I leave this for the MAINTAINER to
fix, since there might be a reason why this flag is ignored.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Alan Douglas <adouglas@cadence.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/cadence/pcie-cadence-ep.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/pci/cadence/pcie-cadence-ep.c b/drivers/pci/cadence/pcie-cadence-ep.c index cef36cd6b710..2905e098678c 100644 --- a/drivers/pci/cadence/pcie-cadence-ep.c +++ b/drivers/pci/cadence/pcie-cadence-ep.c @@ -106,6 +106,9 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, if (is_64bits && (bar & 1)) return -EINVAL; + if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) + epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64; + if (is_64bits && is_prefetch) ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; else if (is_prefetch) |