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authorMinghuan Lian <Minghuan.Lian@freescale.com>2015-10-16 09:19:16 +0200
committerBjorn Helgaas <bhelgaas@google.com>2015-11-02 22:38:38 +0100
commit7af4ce3571931bdc043c4220402262f817b9b968 (patch)
tree8e1a7bd1ffc4c1b10d6c8f472c6015eb1901c3a8 /drivers/pci
parentPCI: layerscape: Remove ls_pcie_establish_link() (diff)
downloadlinux-7af4ce3571931bdc043c4220402262f817b9b968.tar.xz
linux-7af4ce3571931bdc043c4220402262f817b9b968.zip
PCI: layerscape: Ignore PCIe controllers in Endpoint mode
Layerscape PCIe controller supports root complex (RC) and endpoint (EP) modes, which can be set by RCW. If not in RC mode, return -ENODEV without claiming the controller. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/host/pci-layerscape.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
index 6dd44a071240..5eabe9238f0e 100644
--- a/drivers/pci/host/pci-layerscape.c
+++ b/drivers/pci/host/pci-layerscape.c
@@ -47,6 +47,16 @@ struct ls_pcie {
#define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
+static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
+{
+ u32 header_type;
+
+ header_type = ioread8(pcie->dbi + PCI_HEADER_TYPE);
+ header_type &= 0x7f;
+
+ return header_type == PCI_HEADER_TYPE_BRIDGE;
+}
+
static int ls_pcie_link_up(struct pcie_port *pp)
{
u32 state;
@@ -135,6 +145,9 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
return ret;
pcie->index = index[1];
+ if (!ls_pcie_is_bridge(pcie))
+ return -ENODEV;
+
ret = ls_add_pcie_port(pcie);
if (ret < 0)
return ret;