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| author | Damien Le Moal <dlemoal@kernel.org> | 2024-04-13 02:41:19 +0200 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2024-07-10 01:28:27 +0200 |
| commit | c47f90be4c89d14051d43f0c88eafddf67c834ea (patch) | |
| tree | 8efddd7ad60788f860c0017d13b28f9ba7db80e3 /drivers/pci | |
| parent | PCI: dwc: ep: Enforce DWC specific 64-bit BAR limitation (diff) | |
| download | linux-c47f90be4c89d14051d43f0c88eafddf67c834ea.tar.xz linux-c47f90be4c89d14051d43f0c88eafddf67c834ea.zip | |
PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handling
PCIe CEM r5.1, sec 2.9.2, mandates that the PERST# signal must remain
asserted for at least 100 usec (Tperst-clk) after the PCIe reference clock
becomes stable (if a reference clock is supplied), and for at least 100
msec after the power is stable (Tpvperl, defined by the macro
PCIE_T_PVPERL_MS).
Modify rockchip_pcie_host_init_port() to satisfy these constraints by
adding a sleep period before deasserting PERST# using the ep_gpio GPIO.
Since Tperst-clk is the shorter wait time, add an msleep() call for the
longer PCIE_T_PVPERL_MS milliseconds to handle both timing requirements.
Link: https://lore.kernel.org/linux-pci/20240413004120.1099089-2-dlemoal@kernel.org
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/controller/pcie-rockchip-host.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c index 300b9dc85ecc..fc868251e570 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -322,6 +322,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, PCIE_CLIENT_CONFIG); + msleep(PCIE_T_PVPERL_MS); gpiod_set_value_cansleep(rockchip->ep_gpio, 1); /* 500ms timeout value should be enough for Gen1/2 training */ |