diff options
| author | Rob Herring <robh@kernel.org> | 2020-11-05 22:11:45 +0100 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2020-11-19 11:51:40 +0100 |
| commit | 1d567aac46101c8743e49990b94560f86740bb1e (patch) | |
| tree | dc00c61ce7fc2d8a217a313a98ad0c9cbbd31af3 /drivers/pci | |
| parent | PCI: dwc: Add support to program ATU for >4GB memory (diff) | |
| download | linux-1d567aac46101c8743e49990b94560f86740bb1e.tar.xz linux-1d567aac46101c8743e49990b94560f86740bb1e.zip | |
PCI: dwc/intel-gw: Move ATU offset out of driver match data
The ATU offset should be a register range in DT called 'atu', not driver
match data. Any future platforms with a different ATU offset should add
it to their DT.
This is also in preparation to do DBI resource setup in the core DWC
code, so let's move setting atu_base later in intel_pcie_rc_setup().
Link: https://lore.kernel.org/r/20201105211159.1814485-3-robh@kernel.org
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-intel-gw.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c index 5650cb78acba..77ef88333115 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -58,7 +58,6 @@ struct intel_pcie_soc { unsigned int pcie_ver; - unsigned int pcie_atu_offset; u32 num_viewport; }; @@ -155,11 +154,15 @@ static void intel_pcie_init_n_fts(struct dw_pcie *pci) static void intel_pcie_rc_setup(struct intel_pcie_port *lpp) { + struct dw_pcie *pci = &lpp->pci; + + pci->atu_base = pci->dbi_base + 0xC0000; + intel_pcie_ltssm_disable(lpp); intel_pcie_link_setup(lpp); - intel_pcie_init_n_fts(&lpp->pci); - dw_pcie_setup_rc(&lpp->pci.pp); - dw_pcie_upconfig_setup(&lpp->pci); + intel_pcie_init_n_fts(pci); + dw_pcie_setup_rc(&pci->pp); + dw_pcie_upconfig_setup(pci); } static int intel_pcie_ep_rst_init(struct intel_pcie_port *lpp) @@ -425,7 +428,6 @@ static const struct dw_pcie_host_ops intel_pcie_dw_ops = { static const struct intel_pcie_soc pcie_data = { .pcie_ver = 0x520A, - .pcie_atu_offset = 0xC0000, .num_viewport = 3, }; @@ -461,7 +463,6 @@ static int intel_pcie_probe(struct platform_device *pdev) pci->ops = &intel_pcie_ops; pci->version = data->pcie_ver; - pci->atu_base = pci->dbi_base + data->pcie_atu_offset; pp->ops = &intel_pcie_dw_ops; ret = dw_pcie_host_init(pp); |