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| author | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-06 20:36:57 +0200 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-12 05:54:54 +0200 |
| commit | f3eca6c4f42dc2dc057d6ef5d7dae1a5307f4f9f (patch) | |
| tree | 4f7be704175478a6a21bce36084ae07f3eedefa2 /drivers/pci | |
| parent | PCI: keystone: Add local struct device pointers (diff) | |
| download | linux-f3eca6c4f42dc2dc057d6ef5d7dae1a5307f4f9f.tar.xz linux-f3eca6c4f42dc2dc057d6ef5d7dae1a5307f4f9f.zip | |
PCI: keystone: Use generic DesignWare accessors
The dw_pcie_readl_rc() and dw_pcie_writel_rc() interfaces already add in
pp->dbi_base, so use those instead of doing it ourselves in the keystone
driver. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pci-keystone-dw.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-keystone-dw.c index e2c04d1a8a87..ce97816f5d64 100644 --- a/drivers/pci/host/pci-keystone-dw.c +++ b/drivers/pci/host/pci-keystone-dw.c @@ -362,8 +362,8 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) /* Disable BARs for inbound access */ ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base); - writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0); - writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1); + dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, 0); + dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_1, 0); ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base); /* Set outbound translation size per window division */ @@ -461,8 +461,8 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base); /* Enable BAR0 */ - writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0); - writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0); + dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, 1); + dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, SZ_4K - 1); ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base); @@ -470,7 +470,7 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) * For BAR0, just setting bus address for inbound writes (MSI) should * be sufficient. Use physical address to avoid any conflicts. */ - writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0); + dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, ks_pcie->app.start); } /** @@ -478,8 +478,9 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) */ int ks_dw_pcie_link_up(struct pcie_port *pp) { - u32 val = readl(pp->dbi_base + DEBUG0); + u32 val; + val = dw_pcie_readl_rc(pp, DEBUG0); return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; } |