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| author | Agustin Vega-Frias <agustinv@codeaurora.org> | 2017-03-31 20:13:43 +0200 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2017-04-03 19:53:50 +0200 |
| commit | 3071f13d75f627ed8648535815a0506d50cbc6ed (patch) | |
| tree | 86feaf03335af1381fb80d87e956e1957d5d1e37 /drivers/perf/Kconfig | |
| parent | drivers/perf: arm_pmu: split irq request from enable (diff) | |
| download | linux-3071f13d75f627ed8648535815a0506d50cbc6ed.tar.xz linux-3071f13d75f627ed8648535815a0506d50cbc6ed.zip | |
perf: qcom: Add L3 cache PMU driver
This adds a new dynamic PMU to the Perf Events framework to program
and control the L3 cache PMUs in some Qualcomm Technologies SOCs.
The driver supports a distributed cache architecture where the overall
cache for a socket is comprised of multiple slices each with its own PMU.
Access to each individual PMU is provided even though all CPUs share all
the slices. User space needs to aggregate to individual counts to provide
a global picture.
The driver exports formatting and event information to sysfs so it can
be used by the perf user space tools with the syntaxes:
perf stat -a -e l3cache_0_0/read-miss/
perf stat -a -e l3cache_0_0/event=0x21/
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Agustin Vega-Frias <agustinv@codeaurora.org>
[will: fixed sparse issues]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/perf/Kconfig')
| -rw-r--r-- | drivers/perf/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 93651907874f..c436e0d303e7 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -21,6 +21,16 @@ config QCOM_L2_PMU Adds the L2 cache PMU into the perf events subsystem for monitoring L2 cache events. +config QCOM_L3_PMU + bool "Qualcomm Technologies L3-cache PMU" + depends on ARCH_QCOM && ARM64 && PERF_EVENTS && ACPI + select QCOM_IRQ_COMBINER + help + Provides support for the L3 cache performance monitor unit (PMU) + in Qualcomm Technologies processors. + Adds the L3 cache PMU into the perf events subsystem for + monitoring L3 cache events. + config XGENE_PMU depends on PERF_EVENTS && ARCH_XGENE bool "APM X-Gene SoC PMU" |