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| author | Michael Walle <mwalle@kernel.org> | 2023-11-23 12:02:02 +0100 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2023-11-27 13:53:26 +0100 |
| commit | 06f76e464ac81c6915430b7155769ea4ef16efe4 (patch) | |
| tree | b77a1872159d2e685430efe24cc20ca525d0435e /drivers/phy/mediatek | |
| parent | phy: ti: gmii-sel: Fix register offset when parent is not a syscon node (diff) | |
| download | linux-06f76e464ac81c6915430b7155769ea4ef16efe4.tar.xz linux-06f76e464ac81c6915430b7155769ea4ef16efe4.zip | |
phy: mediatek: mipi: mt8183: fix minimal supported frequency
The lowest supported clock frequency of the PHY is 125MHz (see also
mtk_mipi_tx_pll_enable()), but the clamping in .round_rate() has the
wrong minimal value, which will make the .enable() op return -EINVAL on
low frequencies. Fix the minimal clamping value.
Fixes: efda51a58b4a ("drm/mediatek: add mipi_tx driver for mt8183")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20231123110202.2025585-1-mwalle@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/mediatek')
| -rw-r--r-- | drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c index f021ec5a70e5..553725e1269c 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c @@ -100,7 +100,7 @@ static void mtk_mipi_tx_pll_disable(struct clk_hw *hw) static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { - return clamp_val(rate, 50000000, 1600000000); + return clamp_val(rate, 125000000, 1600000000); } static const struct clk_ops mtk_mipi_tx_pll_ops = { |