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author | Bill Huang <bilhuang@nvidia.com> | 2015-06-18 23:28:26 +0200 |
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committer | Thierry Reding <treding@nvidia.com> | 2015-11-20 18:05:04 +0100 |
commit | fde207eb15115f1081e589267ebdf442aa54cda5 (patch) | |
tree | d6f9907076138f33db9691e28d8b6bcfded1a214 /drivers/phy/phy-twl4030-usb.c | |
parent | clk: tegra: pll: Add logic for out-of-table rates for T210 (diff) | |
download | linux-fde207eb15115f1081e589267ebdf442aa54cda5.tar.xz linux-fde207eb15115f1081e589267ebdf442aa54cda5.zip |
clk: tegra: pll: Add code to handle if resets are supported by PLL
If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/phy/phy-twl4030-usb.c')
0 files changed, 0 insertions, 0 deletions