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| author | Alan Douglas <adouglas@cadence.com> | 2018-11-12 17:42:01 +0100 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2018-12-12 05:31:38 +0100 |
| commit | cb96a690724e105f149b27a88d66669c53b01625 (patch) | |
| tree | 80b9c10f42ecb03960bd28a6ea84178e6de47e11 /drivers/phy | |
| parent | phy: core: clean up unused ethernet specific phy modes (diff) | |
| download | linux-cb96a690724e105f149b27a88d66669c53b01625.tar.xz linux-cb96a690724e105f149b27a88d66669c53b01625.zip | |
dt-bindings: phy: Document cadence Sierra PHY bindings
Add DT binding documentation for Sierra PHY. The PHY supports
a number of different protocols, including PCIe and USB.
The PHY lanes may be configured as single or multi-lane links.
Each link is treated as a separate sub-node. For example, if
there are 4 lanes in total the first 2 might be configured as
a multi-lane PCIe link while the other two are single lane
USB links, and in this case there would be 3 sub-nodes.
There are two resets for the PHY block (one for APB register
access, one for the PHY link) and separate resets for each
link. For multi-lane links, the reset corresponds to the
reset line on the master lane, the resets on other lanes
have no effect.
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/phy')
0 files changed, 0 insertions, 0 deletions