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author | Kishon Vijay Abraham I <kishon@ti.com> | 2019-12-16 10:57:00 +0100 |
---|---|---|
committer | Kishon Vijay Abraham I <kishon@ti.com> | 2020-01-08 08:28:06 +0100 |
commit | 372428db44cf8666ff07fa349d305c1be35cb7d4 (patch) | |
tree | 5dd99223b9e714201199c44ab29ce46f1b51b0c2 /drivers/phy | |
parent | dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E (diff) | |
download | linux-372428db44cf8666ff07fa349d305c1be35cb7d4.tar.xz linux-372428db44cf8666ff07fa349d305c1be35cb7d4.zip |
phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources
Certain platforms like TI J721E using Cadence Sierra Serdes
doesn't provide explicit phy_clk and reset (APB reset) control.
Make them optional here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/phy')
-rw-r--r-- | drivers/phy/cadence/phy-cadence-sierra.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index de10402f2931..bed68c25682f 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -193,7 +193,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sp); - sp->clk = devm_clk_get(dev, "phy_clk"); + sp->clk = devm_clk_get_optional(dev, "phy_clk"); if (IS_ERR(sp->clk)) { dev_err(dev, "failed to get clock phy_clk\n"); return PTR_ERR(sp->clk); @@ -205,7 +205,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) return PTR_ERR(sp->phy_rst); } - sp->apb_rst = devm_reset_control_get(dev, "sierra_apb"); + sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); if (IS_ERR(sp->apb_rst)) { dev_err(dev, "failed to get apb reset\n"); return PTR_ERR(sp->apb_rst); |