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| author | Icenowy Zheng <icenowy@aosc.xyz> | 2017-03-25 15:50:10 +0100 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2017-04-10 13:12:57 +0200 |
| commit | 864ebdf0bd4166e64c21e95b72d770eaa33122aa (patch) | |
| tree | 2a3231944e951cb776e3b0a9f23b7d507036c98a /drivers/phy | |
| parent | phy: sun4i-usb: change PHYCTL register clearing code (diff) | |
| download | linux-864ebdf0bd4166e64c21e95b72d770eaa33122aa.tar.xz linux-864ebdf0bd4166e64c21e95b72d770eaa33122aa.zip | |
phy: sun4i-usb: add PHYCTL offset for H3 SoC
The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
register offset missing.
Add it. From the BSP source code, we know that the offset should be
0x10.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/phy-sun4i-usb.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c index 62b4d25448c6..a650f283f6ff 100644 --- a/drivers/phy/phy-sun4i-usb.c +++ b/drivers/phy/phy-sun4i-usb.c @@ -821,6 +821,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { .num_phys = 4, .type = sun8i_h3_phy, .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, .enable_pmu_unk1 = true, }; |