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| author | Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | 2021-10-29 12:39:03 +0200 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2021-11-23 06:51:53 +0100 |
| commit | 1c1597c8027aa4a98a56e8b5b341ddc38451f0e8 (patch) | |
| tree | 1cdfd9d6ab915b8e78f4bcb7c197ebd570da43a3 /drivers/phy | |
| parent | dt-bindings: phy: uniphier-pcie: Add bindings for NX1 SoC (diff) | |
| download | linux-1c1597c8027aa4a98a56e8b5b341ddc38451f0e8.tar.xz linux-1c1597c8027aa4a98a56e8b5b341ddc38451f0e8.zip | |
phy: uniphier-pcie: Add compatible string and SoC-dependent data for NX1 SoC
Add basic support for UniPhier NX1 SoC. This includes a compatible string,
SoC-dependent data, and a function that set to 2-lane mode.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1635503947-18250-5-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/socionext/phy-uniphier-pcie.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c index 6bdbd1f214dd..fde8aac5f4b6 100644 --- a/drivers/phy/socionext/phy-uniphier-pcie.c +++ b/drivers/phy/socionext/phy-uniphier-pcie.c @@ -39,6 +39,10 @@ #define SG_USBPCIESEL 0x590 #define SG_USBPCIESEL_PCIE BIT(0) +/* SC */ +#define SC_US3SRCSEL 0x2244 +#define SC_US3SRCSEL_2LANE GENMASK(9, 8) + #define PCL_PHY_R00 0 #define RX_EQ_ADJ_EN BIT(3) /* enable for EQ adjustment */ #define PCL_PHY_R06 6 @@ -261,6 +265,12 @@ static void uniphier_pciephy_ld20_setmode(struct regmap *regmap) SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE); } +static void uniphier_pciephy_nx1_setmode(struct regmap *regmap) +{ + regmap_update_bits(regmap, SC_US3SRCSEL, + SC_US3SRCSEL_2LANE, SC_US3SRCSEL_2LANE); +} + static const struct uniphier_pciephy_soc_data uniphier_pro5_data = { .is_legacy = true, }; @@ -274,6 +284,11 @@ static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = { .is_legacy = false, }; +static const struct uniphier_pciephy_soc_data uniphier_nx1_data = { + .is_legacy = false, + .set_phymode = uniphier_pciephy_nx1_setmode, +}; + static const struct of_device_id uniphier_pciephy_match[] = { { .compatible = "socionext,uniphier-pro5-pcie-phy", @@ -287,6 +302,10 @@ static const struct of_device_id uniphier_pciephy_match[] = { .compatible = "socionext,uniphier-pxs3-pcie-phy", .data = &uniphier_pxs3_data, }, + { + .compatible = "socionext,uniphier-nx1-pcie-phy", + .data = &uniphier_nx1_data, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, uniphier_pciephy_match); |