diff options
| author | Billy Tsai <billy_tsai@aspeedtech.com> | 2020-12-17 03:49:12 +0100 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2021-01-04 16:02:28 +0100 |
| commit | 92ff62a7bcc17d47c0ce8dddfb7a6e1a2e55ebf4 (patch) | |
| tree | 48e6af7f29e2de311c2e500d82dc74b2a4afd1a1 /drivers/pinctrl/aspeed | |
| parent | pinctrl: ingenic: Rename registers from JZ4760_GPIO_* to JZ4770_GPIO_* (diff) | |
| download | linux-92ff62a7bcc17d47c0ce8dddfb7a6e1a2e55ebf4.tar.xz linux-92ff62a7bcc17d47c0ce8dddfb7a6e1a2e55ebf4.zip | |
pinctrl: aspeed: g6: Fix PWMG0 pinctrl setting
The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from
SCU414 to SCU4B4.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20201217024912.3198-1-billy_tsai@aspeedtech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/aspeed')
| -rw-r--r-- | drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 34803a6c7664..5c1a109842a7 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -347,7 +347,7 @@ FUNC_GROUP_DECL(RMII4, F24, E23, E24, E25, C25, C24, B26, B25, B24); #define D22 40 SIG_EXPR_LIST_DECL_SESG(D22, SD1CLK, SD1, SIG_DESC_SET(SCU414, 8)); -SIG_EXPR_LIST_DECL_SEMG(D22, PWM8, PWM8G0, PWM8, SIG_DESC_SET(SCU414, 8)); +SIG_EXPR_LIST_DECL_SEMG(D22, PWM8, PWM8G0, PWM8, SIG_DESC_SET(SCU4B4, 8)); PIN_DECL_2(D22, GPIOF0, SD1CLK, PWM8); GROUP_DECL(PWM8G0, D22); |