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| author | Linus Walleij <linus.walleij@linaro.org> | 2019-07-09 13:41:53 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2019-07-10 11:19:00 +0200 |
| commit | a1cd6c8b8f03930faf110234fa8366c4ff25085d (patch) | |
| tree | 9b503b0c761d0ef276e70ed3d302b442e6b65045 /drivers/pinctrl/aspeed | |
| parent | pinctrl: baytrail: Use GENMASK() consistently (diff) | |
| download | linux-a1cd6c8b8f03930faf110234fa8366c4ff25085d.tar.xz linux-a1cd6c8b8f03930faf110234fa8366c4ff25085d.zip | |
pinctrl: aspeed: Fix missed include
Some SPDX churn made my fixes drop an important include
from the Aspeed pinctrl header. Fix it up.
Cc: Andrew Jeffery <andrew@aj.id.au>
Reported-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/aspeed')
| -rw-r--r-- | drivers/pinctrl/aspeed/pinctrl-aspeed.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index 9b20b1c03802..b7790395aead 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -16,6 +16,8 @@ #include <linux/pinctrl/pinconf-generic.h> #include <linux/regmap.h> +#include "pinmux-aspeed.h" + /* * The ASPEED SoCs provide typically more than 200 pins for GPIO and other * functions. The SoC function enabled on a pin is determined on a priority |