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authorMika Westerberg <mika.westerberg@linux.intel.com>2017-06-06 15:18:19 +0200
committerLinus Walleij <linus.walleij@linaro.org>2017-06-09 13:03:47 +0200
commit19a8a7771770bd593d582e06b75e86499c1cabc8 (patch)
treefc3f0d96c70646dd016c207d86fd9c1ea651b427 /drivers/pinctrl/intel/Kconfig
parentpinctrl: intel: Make it possible to specify mode per pin in a group (diff)
downloadlinux-19a8a7771770bd593d582e06b75e86499c1cabc8.tar.xz
linux-19a8a7771770bd593d582e06b75e86499c1cabc8.zip
pinctrl: intel: Add Intel Cannon Lake PCH pin controller support
This adds pinctrl/GPIO support for Intel Cannon Lake PCH. The Cannon Lake PCH GPIO is based on newer version of the Intel GPIO hardware. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/intel/Kconfig')
-rw-r--r--drivers/pinctrl/intel/Kconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index 396830a41127..b82d6ff3116f 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -56,6 +56,14 @@ config PINCTRL_BROXTON
Broxton pinctrl driver provides an interface that allows
configuring of SoC pins and using them as GPIOs.
+config PINCTRL_CANNONLAKE
+ tristate "Intel Cannon Lake PCH pinctrl and GPIO driver"
+ depends on ACPI
+ select PINCTRL_INTEL
+ help
+ This pinctrl driver provides an interface that allows configuring
+ of Intel Cannon Lake PCH pins and using them as GPIOs.
+
config PINCTRL_GEMINILAKE
tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
depends on ACPI