diff options
| author | Mika Westerberg <mika.westerberg@linux.intel.com> | 2015-03-30 16:31:49 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2015-04-07 15:15:23 +0200 |
| commit | 7981c0015af26323281c937c8983dfeabc3395fe (patch) | |
| tree | df17a64dda5a262ff3f663c2e9a6d1e481d229ba /drivers/pinctrl/intel/Kconfig | |
| parent | pinctrl: fsl: imx: Check for 0 config register (diff) | |
| download | linux-7981c0015af26323281c937c8983dfeabc3395fe.tar.xz linux-7981c0015af26323281c937c8983dfeabc3395fe.zip | |
pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support
This driver supports pinctrl/GPIO hardware found on Intel Sunrisepoint (a
Skylake PCH) providing users a pinctrl and GPIO interfaces (including GPIO
interrupts).
The driver is split into core and platform parts so that the same core
driver can be reused in other drivers for other Intel GPIO hardware that is
based on the same host controller design.
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/intel/Kconfig')
| -rw-r--r-- | drivers/pinctrl/intel/Kconfig | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index b801d869e91c..fe5e07db0a95 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -25,3 +25,20 @@ config PINCTRL_CHERRYVIEW help Cherryview/Braswell pinctrl driver provides an interface that allows configuring of SoC pins and using them as GPIOs. + +config PINCTRL_INTEL + tristate + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + +config PINCTRL_SUNRISEPOINT + tristate "Intel Sunrisepoint pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver + provides an interface that allows configuring of PCH pins and + using them as GPIOs. |