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| author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2015-06-09 18:47:17 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2015-06-10 14:09:49 +0200 |
| commit | 88b355f1e4e517b636bc5c4b2fb53ec55ccc578d (patch) | |
| tree | 7a52c5c04ec02c3e13a21e7a639b9b7dba9dcd55 /drivers/pinctrl/mvebu | |
| parent | pinctrl: mvebu: armada-39x: normalize ref clock naming (diff) | |
| download | linux-88b355f1e4e517b636bc5c4b2fb53ec55ccc578d.tar.xz linux-88b355f1e4e517b636bc5c4b2fb53ec55ccc578d.zip | |
pinctrl: mvebu: armada-xp: add spi1 function
The latest Armada XP datasheet documents that some of the MPP pins can
be used to access the second SPI bus, labelled 'spi1'. This commit
adds the corresponding pins in the pinctrl driver and its DT binding
documentation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/mvebu')
| -rw-r--r-- | drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 74ff2118a9ed..467446220c98 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -109,11 +109,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "txd5", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txd0", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "mosi", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d13", V_MV78230_PLUS)), MPP_MODE(14, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "txd6", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txd1", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "sck", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d14", V_MV78230_PLUS)), MPP_MODE(15, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), @@ -124,11 +126,13 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "txclk", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txd3", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "cs0", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d16", V_MV78230_PLUS)), MPP_MODE(17, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "ge0", "col", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "ge1", "txctl", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi1", "miso", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "d17", V_MV78230_PLUS)), MPP_MODE(18, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), @@ -239,14 +243,16 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "spi0", "cs1", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs1", V_MV78230_PLUS)), MPP_MODE(41, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "spi0", "cs2", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs2", V_MV78230_PLUS)), MPP_MODE(42, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS), @@ -258,33 +264,38 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs3", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs3", V_MV78230_PLUS)), MPP_MODE(44, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs4", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs4", V_MV78230_PLUS)), MPP_MODE(45, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs5", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs5", V_MV78230_PLUS)), MPP_MODE(46, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs6", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs6", V_MV78230_PLUS)), MPP_MODE(47, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x3, "spi0", "cs7", V_MV78230_PLUS), MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS), - MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x6, "spi1", "cs7", V_MV78230_PLUS)), MPP_MODE(48, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS), |