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| author | Daniel Kurtz <djkurtz@chromium.org> | 2018-07-17 03:07:41 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2018-07-29 22:20:15 +0200 |
| commit | 1766e4b7047acf44cdd15aaeb1d63ed76ee78492 (patch) | |
| tree | b75923554ef9e458b40f63d9a109f84f076d8865 /drivers/pinctrl/pinctrl-amd.h | |
| parent | pinctrl: stm32: add syscfg mask parameter (diff) | |
| download | linux-1766e4b7047acf44cdd15aaeb1d63ed76ee78492.tar.xz linux-1766e4b7047acf44cdd15aaeb1d63ed76ee78492.zip | |
pinctrl/amd: fix gpio irq level in debugfs
According to the AMD BKDG, the GPIO ActiveLevel bits (10:9) map to:
00 Active High
01 Active Low
10 Active on both edges iff LevelTrig (bit 8) == 0
11 Reserved
The current code has a bug where it interprets 00 => Active Low, and
01 => Active High.
Fix the bug, restrict "Active on both" to just the edge trigger case, and
refactor a bit to make the logic more readable.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-amd.h')
| -rw-r--r-- | drivers/pinctrl/pinctrl-amd.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index 8fa453a59da5..22af7edfdb38 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -54,6 +54,10 @@ #define ACTIVE_LEVEL_MASK 0x3UL #define DRV_STRENGTH_SEL_MASK 0x3UL +#define ACTIVE_LEVEL_HIGH 0x0UL +#define ACTIVE_LEVEL_LOW 0x1UL +#define ACTIVE_LEVEL_BOTH 0x2UL + #define DB_TYPE_NO_DEBOUNCE 0x0UL #define DB_TYPE_PRESERVE_LOW_GLITCH 0x1UL #define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL |