pinctrl: Pass all configs to driver on pin_config_set()

When setting pin configuration in the pinctrl framework, pin_config_set() or
pin_config_group_set() is called in a loop to set one configuration at a time
for the specified pin or group.

This patch 1) removes the loop and 2) changes the API to pass the whole pin
config array to the driver.  It is now up to the driver to loop through the
configs.  This allows the driver to potentially combine configs and reduce the
number of writes to pin config registers.

All c files changed have been build-tested to verify the change compiles and
that the corresponding .o is successfully generated.

Signed-off-by: Sherman Yin <syin@broadcom.com>
Reviewed-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

1 files changed, 72 insertions, 62 deletions

diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c
index 9550c33b2544..82638fac3cfa 100644
--- a/drivers/pinctrl/pinctrl-palmas.c
+++ b/drivers/pinctrl/pinctrl-palmas.c
@@ -854,17 +854,19 @@ static int palmas_pinconf_get(struct pinctrl_dev *pctldev,
 }
 
 static int palmas_pinconf_set(struct pinctrl_dev *pctldev,
-			unsigned pin, unsigned long config)
+			unsigned pin, unsigned long *configs,
+			unsigned num_configs)
 {
 	struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
-	enum pin_config_param param = pinconf_to_config_param(config);
-	u16 param_val = pinconf_to_config_argument(config);
+	enum pin_config_param param;
+	u16 param_val;
 	const struct palmas_pingroup *g;
 	const struct palmas_pin_info *opt;
 	int ret;
 	int base, add, mask;
 	int rval;
 	int group_nr;
+	int i;
 
 	for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
 		if (pci->pin_groups[group_nr].pins[0] == pin)
@@ -885,70 +887,77 @@ static int palmas_pinconf_set(struct pinctrl_dev *pctldev,
 		return -ENOTSUPP;
 	}
 
-	switch (param) {
-	case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
-		return 0;
-	case PIN_CONFIG_BIAS_DISABLE:
-	case PIN_CONFIG_BIAS_PULL_UP:
-	case PIN_CONFIG_BIAS_PULL_DOWN:
-		if (!opt->pud_info) {
-			dev_err(pci->dev,
-				"PULL control not supported for pin %s\n",
-				g->name);
-			return -ENOTSUPP;
-		}
-		base = opt->pud_info->pullup_dn_reg_base;
-		add = opt->pud_info->pullup_dn_reg_add;
-		mask = opt->pud_info->pullup_dn_mask;
-
-		if (param == PIN_CONFIG_BIAS_DISABLE)
-			rval = opt->pud_info->normal_val;
-		else if (param == PIN_CONFIG_BIAS_PULL_UP)
-			rval = opt->pud_info->pull_up_val;
-		else
-			rval = opt->pud_info->pull_dn_val;
+	for (i = 0; i < num_configs; i++) {
+		param = pinconf_to_config_param(configs[i]);
+		param_val = pinconf_to_config_argument(configs[i]);
+
+		switch (param) {
+		case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
+			return 0;
+		case PIN_CONFIG_BIAS_DISABLE:
+		case PIN_CONFIG_BIAS_PULL_UP:
+		case PIN_CONFIG_BIAS_PULL_DOWN:
+			if (!opt->pud_info) {
+				dev_err(pci->dev,
+					"PULL control not supported for pin %s\n",
+					g->name);
+				return -ENOTSUPP;
+			}
+			base = opt->pud_info->pullup_dn_reg_base;
+			add = opt->pud_info->pullup_dn_reg_add;
+			mask = opt->pud_info->pullup_dn_mask;
+
+			if (param == PIN_CONFIG_BIAS_DISABLE)
+				rval = opt->pud_info->normal_val;
+			else if (param == PIN_CONFIG_BIAS_PULL_UP)
+				rval = opt->pud_info->pull_up_val;
+			else
+				rval = opt->pud_info->pull_dn_val;
+
+			if (rval < 0) {
+				dev_err(pci->dev,
+					"PULL control not supported for pin %s\n",
+					g->name);
+				return -ENOTSUPP;
+			}
+			break;
 
-		if (rval < 0) {
-			dev_err(pci->dev,
-				"PULL control not supported for pin %s\n",
-				g->name);
+		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+			if (!opt->od_info) {
+				dev_err(pci->dev,
+					"OD control not supported for pin %s\n",
+					g->name);
+				return -ENOTSUPP;
+			}
+			base = opt->od_info->od_reg_base;
+			add = opt->od_info->od_reg_add;
+			mask = opt->od_info->od_mask;
+			if (param_val == 0)
+				rval = opt->od_info->od_disable;
+			else
+				rval = opt->od_info->od_enable;
+			if (rval < 0) {
+				dev_err(pci->dev,
+					"OD control not supported for pin %s\n",
+					g->name);
+				return -ENOTSUPP;
+			}
+			break;
+		default:
+			dev_err(pci->dev, "Properties not supported\n");
 			return -ENOTSUPP;
 		}
-		break;
 
-	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
-		if (!opt->od_info) {
-			dev_err(pci->dev,
-				"OD control not supported for pin %s\n",
-				g->name);
-			return -ENOTSUPP;
-		}
-		base = opt->od_info->od_reg_base;
-		add = opt->od_info->od_reg_add;
-		mask = opt->od_info->od_mask;
-		if (param_val == 0)
-			rval = opt->od_info->od_disable;
-		else
-			rval = opt->od_info->od_enable;
-		if (rval < 0) {
-			dev_err(pci->dev,
-				"OD control not supported for pin %s\n",
-				g->name);
-			return -ENOTSUPP;
+		dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n",
+				__func__, base, add, mask, rval);
+		ret = palmas_update_bits(pci->palmas, base, add, mask, rval);
+		if (ret < 0) {
+			dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
+				add, ret);
+			return ret;
 		}
-		break;
-	default:
-		dev_err(pci->dev, "Properties not supported\n");
-		return -ENOTSUPP;
-	}
+	} /* for each config */
 
-	dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n",
-			__func__, base, add, mask, rval);
-	ret = palmas_update_bits(pci->palmas, base, add, mask, rval);
-	if (ret < 0) {
-		dev_err(pci->dev, "Reg 0x%02x update failed: %d\n", add, ret);
-		return ret;
-	}
 	return 0;
 }
 
@@ -960,7 +969,8 @@ static int palmas_pinconf_group_get(struct pinctrl_dev *pctldev,
 }
 
 static int palmas_pinconf_group_set(struct pinctrl_dev *pctldev,
-				unsigned group, unsigned long config)
+				unsigned group, unsigned long *configs,
+				unsigned num_configs)
 {
 	dev_err(pctldev->dev, "palmas_pinconf_group_set op not supported\n");
 	return -ENOTSUPP;