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authorJianqun Xu <jay.xu@rock-chips.com>2021-08-16 03:21:23 +0200
committerLinus Walleij <linus.walleij@linaro.org>2021-08-17 01:01:50 +0200
commit3bcbd1a85b68e5f864029fd6f0bb0bcc8e2f1082 (patch)
treec8492efb147582dee242a0cf20bb2390730e03ff /drivers/pinctrl/pinctrl-rockchip.h
parentgpio/rockchip: use struct rockchip_gpio_regs for gpio controller (diff)
downloadlinux-3bcbd1a85b68e5f864029fd6f0bb0bcc8e2f1082.tar.xz
linux-3bcbd1a85b68e5f864029fd6f0bb0bcc8e2f1082.zip
gpio/rockchip: support next version gpio controller
The next version gpio controller on SoCs like rk3568 have more write mask bits for registers. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210816012123.1119179-1-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-rockchip.h')
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h
index 1b774b6bbc3e..589d4d2a98c9 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -121,6 +121,7 @@ struct rockchip_drv {
* @reg_base: register base of the gpio bank
* @regmap_pull: optional separate register for additional pull settings
* @clk: clock of the gpio bank
+ * @db_clk: clock of the gpio debounce
* @irq: interrupt of the gpio bank
* @saved_masks: Saved content of GPIO_INTEN at suspend time.
* @pin_base: first pin number
@@ -146,6 +147,7 @@ struct rockchip_pin_bank {
void __iomem *reg_base;
struct regmap *regmap_pull;
struct clk *clk;
+ struct clk *db_clk;
int irq;
u32 saved_masks;
u32 pin_base;