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authorLinus Torvalds <torvalds@linux-foundation.org>2017-01-05 19:36:56 +0100
committerLinus Torvalds <torvalds@linux-foundation.org>2017-01-05 19:36:56 +0100
commitc433eb70f37de2514f3ae3d43dd7e4a75493fe48 (patch)
treec2bba1a4b490ef8787ec7da079f8d1d22f123c80 /drivers/pinctrl/samsung/pinctrl-exynos.h
parentMerge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm... (diff)
parentpinctrl: samsung: Fix the width of PINCFG_TYPE_DRV bitfields for Exynos5433 (diff)
downloadlinux-c433eb70f37de2514f3ae3d43dd7e4a75493fe48.tar.xz
linux-c433eb70f37de2514f3ae3d43dd7e4a75493fe48.zip
Merge tag 'pinctrl-v4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij: "Three small pin control fixes for the v4.10 series. Very little to say about them, just driver fixes. - one fix to the AMD pinctrl ACPI glue - fix requests on the Meson driver - fix bitfield widths on Samsungs Exynos 5433" * tag 'pinctrl-v4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: samsung: Fix the width of PINCFG_TYPE_DRV bitfields for Exynos5433 pinctrl: meson: fix gpio request disabling other modes pinctrl/amd: Set the level based on ACPI tables
Diffstat (limited to 'drivers/pinctrl/samsung/pinctrl-exynos.h')
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.h31
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 5821525a2c84..a473092fb8d2 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -90,6 +90,37 @@
.pctl_res_idx = pctl_idx, \
} \
+#define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \
+ { \
+ .type = &exynos5433_bank_type_off, \
+ .pctl_offset = reg, \
+ .nr_pins = pins, \
+ .eint_type = EINT_TYPE_GPIO, \
+ .eint_offset = offs, \
+ .name = id \
+ }
+
+#define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \
+ { \
+ .type = &exynos5433_bank_type_alive, \
+ .pctl_offset = reg, \
+ .nr_pins = pins, \
+ .eint_type = EINT_TYPE_WKUP, \
+ .eint_offset = offs, \
+ .name = id \
+ }
+
+#define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
+ { \
+ .type = &exynos5433_bank_type_alive, \
+ .pctl_offset = reg, \
+ .nr_pins = pins, \
+ .eint_type = EINT_TYPE_WKUP, \
+ .eint_offset = offs, \
+ .name = id, \
+ .pctl_res_idx = pctl_idx, \
+ } \
+
/**
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
* generated by the external wakeup interrupt controller.