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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-05-01 20:28:03 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-05-01 20:28:03 +0200 |
| commit | ba6728f596a60c4b161722c825883692a3606011 (patch) | |
| tree | 4ad271da44350d126ebd871c5dca0cc4caeaded2 /drivers/pinctrl/sh-pfc/pfc-r8a7790.c | |
| parent | Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/... (diff) | |
| parent | sh-pfc: r8a7791: Fix definition of MOD_SEL3 (diff) | |
| download | linux-ba6728f596a60c4b161722c825883692a3606011.tar.xz linux-ba6728f596a60c4b161722c825883692a3606011.zip | |
Merge tag 'pinctrl-v3.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
"Here is a small set of pin control fixes for the v3.15 series. All
are individual driver fixes and quite self-contained. One of them
tagged for stable.
- Signedness bug in the TB10x
- GPIO inversion fix for the AS3722
- Clear pending pin interrups enabled in the bootloader in the
pinctrl-single driver
- Minor pin definition fixes for the PFC/Renesas driver"
* tag 'pinctrl-v3.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
sh-pfc: r8a7791: Fix definition of MOD_SEL3
sh-pfc: r8a7790: Fix definition of IPSR5
pinctrl: single: Clear pin interrupts enabled by bootloader
pinctrl: as3722: fix handling of GPIO invert bit
pinctrl/TB10x: Fix signedness bug
Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-r8a7790.c')
| -rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 48093719167a..f5cd3f961808 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -4794,8 +4794,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_MSIOF0_SCK_B, 0, /* IP5_23_21 [3] */ FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, - FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, - FN_IERX_C, 0, + FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, /* IP5_20_18 [3] */ FN_WE0_N, FN_IECLK, FN_CAN_CLK, FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, |