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author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2018-02-16 15:25:40 +0100 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-02-20 19:02:56 +0100 |
commit | 5722110e2f8ecf1cf8dac7b0c3c864c5fcf5491f (patch) | |
tree | d5114ae239f812628e6b0d94e7d0d39c030103c8 /drivers/pinctrl/sh-pfc/pfc-r8a7795.c | |
parent | pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL register pin assignment for ND... (diff) | |
download | linux-5722110e2f8ecf1cf8dac7b0c3c864c5fcf5491f.tar.xz linux-5722110e2f8ecf1cf8dac7b0c3c864c5fcf5491f.zip |
pinctrl: sh-pfc: r8a7795: Add HDMI pins, groups and functions
This patch adds HDMI0 CEC pin, group and function to the R8A7795 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: fixed typo in comment]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-r8a7795.c')
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index edbf136b6261..424ba2263aed 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -2128,6 +2128,22 @@ static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +/* - HDMI ------------------------------------------------------------------- */ +static const unsigned int hdmi0_cec_pins[] = { + /* HDMI0_CEC */ + RCAR_GP_PIN(7, 2), +}; +static const unsigned int hdmi0_cec_mux[] = { + HDMI0_CEC_MARK, +}; +static const unsigned int hdmi1_cec_pins[] = { + /* HDMI1_CEC */ + RCAR_GP_PIN(7, 3), +}; +static const unsigned int hdmi1_cec_mux[] = { + HDMI1_CEC_MARK, +}; + /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { /* RX, TX */ @@ -3955,6 +3971,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(hdmi0_cec), + SH_PFC_PIN_GROUP(hdmi1_cec), SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -4305,6 +4323,14 @@ static const char * const du_groups[] = { "du_disp", }; +static const char * const hdmi0_groups[] = { + "hdmi0_cec", +}; + +static const char * const hdmi1_groups[] = { + "hdmi1_cec", +}; + static const char * const hscif0_groups[] = { "hscif0_data", "hscif0_clk", @@ -4672,6 +4698,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(hdmi0), + SH_PFC_FUNCTION(hdmi1), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), |