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authorLinus Walleij <linus.walleij@linaro.org>2022-11-28 21:23:20 +0100
committerLinus Walleij <linus.walleij@linaro.org>2022-11-28 21:23:20 +0100
commite7d0040b4359815095a63e0297b8aa0ae8695b08 (patch)
tree1fc6759ad3a53bf3bbadbc2905b66ff06eddfb78 /drivers/pinctrl
parentpinctrl: sunxi: d1: Add CAN bus pinmuxes (diff)
parentpinctrl: intel: Enumerate PWM device when community has a capability (diff)
downloadlinux-e7d0040b4359815095a63e0297b8aa0ae8695b08.tar.xz
linux-e7d0040b4359815095a63e0297b8aa0ae8695b08.zip
Merge tag 'intel-pinctrl-v6.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.2-2 * Enable PWM feature on Intel pin control IPs The following is an automated git shortlog grouped by driver: intel: - Enumerate PWM device when community has a capability pwm: - lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe() - lpss: Allow other drivers to enable PWM LPSS - lpss: Include headers we are the direct user of - lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS - Add a stub for devm_pwmchip_add()
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 6e630e87fed6..921382fc5fdf 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -24,6 +24,8 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_data/x86/pwm-lpss.h>
+
#include "../core.h"
#include "pinctrl-intel.h"
@@ -49,6 +51,8 @@
#define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
#define PADOWN_GPP(p) ((p) / 8)
+#define PWMC 0x204
+
/* Offset from pad_regs */
#define PADCFG0 0x000
#define PADCFG0_RXEVCFG_SHIFT 25
@@ -1502,6 +1506,27 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
return 0;
}
+static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl,
+ struct intel_community *community)
+{
+ static const struct pwm_lpss_boardinfo info = {
+ .clk_rate = 19200000,
+ .npwm = 1,
+ .base_unit_bits = 22,
+ .bypass = true,
+ };
+ struct pwm_lpss_chip *pwm;
+
+ if (!(community->features & PINCTRL_FEATURE_PWM))
+ return 0;
+
+ if (!IS_REACHABLE(CONFIG_PWM_LPSS))
+ return 0;
+
+ pwm = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info);
+ return PTR_ERR_OR_ZERO(pwm);
+}
+
static int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data)
{
@@ -1588,6 +1613,10 @@ static int intel_pinctrl_probe(struct platform_device *pdev,
ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
if (ret)
return ret;
+
+ ret = intel_pinctrl_probe_pwm(pctrl, community);
+ if (ret)
+ return ret;
}
irq = platform_get_irq(pdev, 0);