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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2023-09-29 07:39:03 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-13 09:38:05 +0200 |
| commit | 35a3610e5a2407913dd6505de06975ba5056af9e (patch) | |
| tree | 5e67264e2b1eebec2ef6c79a065d1ea1492c1846 /drivers/pinctrl | |
| parent | pinctrl: renesas: rzg2l: Adapt for different SD/PWPR register offsets (diff) | |
| download | linux-35a3610e5a2407913dd6505de06975ba5056af9e.tar.xz linux-35a3610e5a2407913dd6505de06975ba5056af9e.zip | |
pinctrl: renesas: rzg2l: Adapt function number for RZ/G3S
On RZ/G3S PFC register allow setting 8 functions for individual ports
(function1 to function8). For function1 the register need to be
configured with 0, for function8 the register need to be configured with
7. We cannot use zero based addressing when requesting functions from
different code places as the documentation
(RZG3S_pinfunction_List_r1.0.xlsx) states explicitly that function0 is
GPIO.
Add a new member to struct rzg2l_hwcfg that will keep the offset that
needs to be substracted before applying a value to a PFC register.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-17-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/renesas/pinctrl-rzg2l.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index a5d0a5c32644..805280dfd697 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -136,9 +136,11 @@ struct rzg2l_register_offsets { /** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets + * @func_base: base number for port function (see register PFC) */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; + u8 func_base; }; struct rzg2l_dedicated_configs { @@ -221,6 +223,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned int group_selector) { struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct function_desc *func; unsigned int i, *psel_val; struct group_desc *group; @@ -242,9 +245,9 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", - RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i]); + RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); - rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i]); + rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); } return 0; |