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authorMaxime Ripard <maxime.ripard@free-electrons.com>2013-02-03 12:10:11 +0100
committerLinus Walleij <linus.walleij@linaro.org>2013-02-05 17:32:29 +0100
commita0d72094f0abad3cbeeed618d24fd0ce1968d1a8 (patch)
treefea531dff6651259dcf4f65a4b809517d841fd44 /drivers/pinctrl
parentARM: sunxi: Add the pin groups for UART0 and UART1 on sun4i (diff)
downloadlinux-a0d72094f0abad3cbeeed618d24fd0ce1968d1a8.tar.xz
linux-a0d72094f0abad3cbeeed618d24fd0ce1968d1a8.zip
pinctrl: sunxi: add of_xlate function
Since the pin controller of sunxi chips is represented as a single bank in the driver. Since this is neither convenient nor represented that way in the datasheets, define a custom of_xlate function with the layout <bank pin flag> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/pinctrl-sunxi.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index e4d32c67dcbb..80b11e3415bc 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -1261,6 +1261,24 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
writel((value & DATA_PINS_MASK) << index, pctl->membase + reg);
}
+static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
+ const struct of_phandle_args *gpiospec,
+ u32 *flags)
+{
+ int pin, base;
+
+ base = PINS_PER_BANK * gpiospec->args[0];
+ pin = base + gpiospec->args[1];
+
+ if (pin > (gc->base + gc->ngpio))
+ return -EINVAL;
+
+ if (flags)
+ *flags = gpiospec->args[2];
+
+ return pin;
+}
+
static struct gpio_chip sunxi_pinctrl_gpio_chip = {
.owner = THIS_MODULE,
.request = sunxi_pinctrl_gpio_request,
@@ -1269,6 +1287,8 @@ static struct gpio_chip sunxi_pinctrl_gpio_chip = {
.direction_output = sunxi_pinctrl_gpio_direction_output,
.get = sunxi_pinctrl_gpio_get,
.set = sunxi_pinctrl_gpio_set,
+ .of_xlate = sunxi_pinctrl_gpio_of_xlate,
+ .of_gpio_n_cells = 3,
.can_sleep = 0,
};