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authorVadim Pasternak <vadimp@nvidia.com>2023-08-22 13:34:38 +0200
committerHans de Goede <hdegoede@redhat.com>2023-08-23 17:31:27 +0200
commit59b96ea4c220f41837b183697def20aa9ec89857 (patch)
tree60112b67971a71d2a872366100e76a6fcd2b0091 /drivers/platform/x86
parentplatform: mellanox: Add field upgrade capability register (diff)
downloadlinux-59b96ea4c220f41837b183697def20aa9ec89857.tar.xz
linux-59b96ea4c220f41837b183697def20aa9ec89857.zip
platform: mellanox: Modify reset causes description
For system of classes VMOD0005, VMOD0010: - remove "reset_from_comex", since this cause doesn't define specific reason. - add more specific reason "reset_sw_reset", which is set along with removed "reset_from_comex". Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20230822113451.13785-4-vadimp@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/platform/x86')
-rw-r--r--drivers/platform/x86/mlx-platform.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c
index 647a10252c2f..5b0579752afb 100644
--- a/drivers/platform/x86/mlx-platform.c
+++ b/drivers/platform/x86/mlx-platform.c
@@ -3557,12 +3557,6 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
.mode = 0444,
},
{
- .label = "reset_from_comex",
- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
- .mask = GENMASK(7, 0) & ~BIT(4),
- .mode = 0444,
- },
- {
.label = "reset_from_asic",
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
.mask = GENMASK(7, 0) & ~BIT(5),
@@ -3581,6 +3575,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
.mode = 0444,
},
{
+ .label = "reset_sw_reset",
+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
+ .mask = GENMASK(7, 0) & ~BIT(0),
+ .mode = 0444,
+ },
+ {
.label = "reset_comex_pwr_fail",
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
.mask = GENMASK(7, 0) & ~BIT(3),