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authorYash Shah <yash.shah@sifive.com>2020-02-20 06:15:19 +0100
committerPalmer Dabbelt <palmerdabbelt@google.com>2020-05-21 00:05:10 +0200
commit4a3a37331248d85df9e05e9b1d8210dc5ec81f4e (patch)
treee69c611a64e0c6652aa0744119b2efd84e1baeb0 /drivers/pwm/pwm-atmel.c
parentriscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure (diff)
downloadlinux-4a3a37331248d85df9e05e9b1d8210dc5ec81f4e.tar.xz
linux-4a3a37331248d85df9e05e9b1d8210dc5ec81f4e.zip
riscv: Add support to determine no. of L2 cache way enabled
In order to determine the number of L2 cache ways enabled at runtime, implement a private attribute ("number_of_ways_enabled"). Reading this attribute returns the number of enabled L2 cache ways at runtime. Using riscv_set_cacheinfo_ops() hook a custom function, that returns this private attribute, to the generic ops structure which is used by cache_get_priv_group() in cacheinfo framework. Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'drivers/pwm/pwm-atmel.c')
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