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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2019-06-12 21:59:01 +0200 |
|---|---|---|
| committer | Thierry Reding <thierry.reding@gmail.com> | 2019-06-26 11:39:08 +0200 |
| commit | 33cefd84d26b59e071b3172b0e3ca979163f39eb (patch) | |
| tree | d42b6ae807f266d93781788daba100529219761f /drivers/pwm/pwm-meson.c | |
| parent | pwm: meson: Use GENMASK and FIELD_PREP for the lo and hi values (diff) | |
| download | linux-33cefd84d26b59e071b3172b0e3ca979163f39eb.tar.xz linux-33cefd84d26b59e071b3172b0e3ca979163f39eb.zip | |
pwm: meson: Change MISC_CLK_SEL_WIDTH to MISC_CLK_SEL_MASK
MISC_CLK_SEL_WIDTH is only used in one place where it's converted into
a bit-mask. Rename and change the macro to be a bit-mask so that
conversion is not needed anymore. No functional changes intended.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/pwm/pwm-meson.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index ec4407ec174d..3f78f8d643d6 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -33,7 +33,7 @@ #define MISC_A_CLK_DIV_SHIFT 8 #define MISC_B_CLK_SEL_SHIFT 6 #define MISC_A_CLK_SEL_SHIFT 4 -#define MISC_CLK_SEL_WIDTH 2 +#define MISC_CLK_SEL_MASK 0x3 #define MISC_B_EN BIT(1) #define MISC_A_EN BIT(0) @@ -472,7 +472,7 @@ static int meson_pwm_init_channels(struct meson_pwm *meson, channel->mux.reg = meson->base + REG_MISC_AB; channel->mux.shift = mux_reg_shifts[i]; - channel->mux.mask = BIT(MISC_CLK_SEL_WIDTH) - 1; + channel->mux.mask = MISC_CLK_SEL_MASK; channel->mux.flags = 0; channel->mux.lock = &meson->lock; channel->mux.table = NULL; |