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| author | Chaitra P B <chaitra.basappa@broadcom.com> | 2018-05-31 12:34:51 +0200 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2018-06-19 03:05:32 +0200 |
| commit | 2b48be65685a23f4ffc7a06858992bc31e98e198 (patch) | |
| tree | a2843d1c320e2b0ca6882fafe642160cbf96d2eb /drivers/scsi/mpt3sas/mpt3sas_base.h | |
| parent | scsi: mpt3sas: Fix, False timeout prints for ioctl and other internal command... (diff) | |
| download | linux-2b48be65685a23f4ffc7a06858992bc31e98e198.tar.xz linux-2b48be65685a23f4ffc7a06858992bc31e98e198.zip | |
scsi: mpt3sas: As per MPI-spec, use combined reply queue for SAS3.5 controllers when HBA supports more than 16 MSI-x vectors.
Presently driver is using combined reply queue feature when MSI-x vectors >
8 for both SAS3 and SAS3.5 controllers. But as per MPI-spec,
1. For SAS3 controllers, driver should use combined reply queue when HBA
supports more than 8 MSI-x vectors.
2. For SAS3.5 controllers, driver should use combined reply queue when HBA
supports more than 16 MSI-x vectors.
Modified driver code to use combined reply queue for SAS3 controllers when
HBA supports > 8 MSI-x vectors and for SAS3.5 controllers when HBA supports
> 16 MSI-x vectors.
Signed-off-by: Chaitra P B <chaitra.basappa@broadcom.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/scsi/mpt3sas/mpt3sas_base.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index ec222add0bb5..3d49eadeb789 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -323,6 +323,7 @@ * There are twelve Supplemental Reply Post Host Index Registers * and each register is at offset 0x10 bytes from the previous one. */ +#define MAX_COMBINED_MSIX_VECTORS(gen35) ((gen35 == 1) ? 16 : 8) #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G3 12 #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G35 16 #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET (0x10) |