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| author | Guennadi Liakhovetski <g.liakhovetski@gmx.de> | 2007-05-04 22:59:40 +0200 |
|---|---|---|
| committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2007-05-06 16:33:21 +0200 |
| commit | 46e5ba2b644d1c7be1253ec32e7cd6ab1dcdf790 (patch) | |
| tree | 2004e75a362b31fd710c57153337995484a5a1c4 /drivers/scsi/tmscsim.h | |
| parent | [SCSI] tmscsim: remove long dead DMA_INT (diff) | |
| download | linux-46e5ba2b644d1c7be1253ec32e7cd6ab1dcdf790.tar.xz linux-46e5ba2b644d1c7be1253ec32e7cd6ab1dcdf790.zip | |
[SCSI] tmscsim: remove bogus endianness conversions
cpu_to_le32 endianness conversions in tmscsim.c, followed by
arithmetic operations don't look correct. Besides, {in,out}[wl]
already perform the necessary conversions. Further, bus addresses
of request buffers are guaranteed to be (mapped) under 4G by
current scsi- and block-layer defaults. This could be explicitly
enforced by using blk_queue_bounce_limit(), which, however,
doesn't seem to be the common practice among SCSI drivers.
Signed-off-by: G. Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/scsi/tmscsim.h')
| -rw-r--r-- | drivers/scsi/tmscsim.h | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/drivers/scsi/tmscsim.h b/drivers/scsi/tmscsim.h index 9b66fa8d38d9..c3d8c80cfb38 100644 --- a/drivers/scsi/tmscsim.h +++ b/drivers/scsi/tmscsim.h @@ -19,14 +19,6 @@ #define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */ -#define pci_dma_lo32(a) (a & 0xffffffff) - -typedef u8 UCHAR; /* 8 bits */ -typedef u16 USHORT; /* 16 bits */ -typedef u32 UINT; /* 32 bits */ -typedef unsigned long ULONG; /* 32/64 bits */ - - /* ;----------------------------------------------------------------------- ; SCSI Request Block @@ -43,7 +35,9 @@ struct scatterlist *pSegmentList; struct scatterlist Segmentx; /* make a one entry of S/G list table */ -unsigned long SGBusAddr; /*;a segment starting address as seen by AM53C974A*/ +unsigned long SGBusAddr; /*;a segment starting address as seen by AM53C974A + in CPU endianness. We're only getting 32-bit bus + addresses by default */ unsigned long SGToBeXferLen; /*; to be xfer length */ unsigned long TotalXferredLen; unsigned long SavedTotXLen; |