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| author | Stanley Chu <stanley.chu@mediatek.com> | 2019-12-30 06:32:27 +0100 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2020-01-03 03:57:45 +0100 |
| commit | 97347214bce8d740ce4d64e22783b50384cd2e6f (patch) | |
| tree | 4d0a30a52129138a765fdd3d0a2b30963708f4df /drivers/scsi/ufs/ufs-mediatek.h | |
| parent | scsi: ufs-mediatek: add device reset implementation (diff) | |
| download | linux-97347214bce8d740ce4d64e22783b50384cd2e6f.tar.xz linux-97347214bce8d740ce4d64e22783b50384cd2e6f.zip | |
scsi: ufs-mediatek: introduce reference clock control
Introduce reference clock control in MediaTek Chipset in order to disable
it if it is not necessary by UFS device to save system power.
Currently reference clock can be disabled during system suspend, runtime
suspend and clock-gating after link enters hibernate state.
Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Avri Altman <avri.altman@wdc.com>
Cc: Bart Van Assche <bvanassche@acm.org>
Cc: Bean Huo <beanhuo@micron.com>
Cc: Can Guo <cang@codeaurora.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/1577683950-1702-4-git-send-email-stanley.chu@mediatek.com
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/ufs/ufs-mediatek.h')
| -rw-r--r-- | drivers/scsi/ufs/ufs-mediatek.h | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h index ce68ce25fdd7..31b7fead19eb 100644 --- a/drivers/scsi/ufs/ufs-mediatek.h +++ b/drivers/scsi/ufs/ufs-mediatek.h @@ -10,6 +10,22 @@ #include <linux/soc/mediatek/mtk_sip_svc.h> /* + * Vendor specific UFSHCI Registers + */ +#define REG_UFS_REFCLK_CTRL 0x144 + +/* + * Ref-clk control + * + * Values for register REG_UFS_REFCLK_CTRL + */ +#define REFCLK_RELEASE 0x0 +#define REFCLK_REQUEST BIT(0) +#define REFCLK_ACK BIT(1) + +#define REFCLK_REQ_TIMEOUT_MS 3 + +/* * Vendor specific pre-defined parameters */ #define UFS_MTK_LIMIT_NUM_LANES_RX 1 @@ -35,8 +51,9 @@ /* * SiP commands */ -#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) -#define UFS_MTK_SIP_DEVICE_RESET BIT(1) +#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276) +#define UFS_MTK_SIP_DEVICE_RESET BIT(1) +#define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3) /* * VS_DEBUGCLOCKENABLE @@ -57,6 +74,7 @@ enum { struct ufs_mtk_host { struct ufs_hba *hba; struct phy *mphy; + bool ref_clk_enabled; }; #endif /* !_UFS_MEDIATEK_H */ |