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authorGabriel Fernandez <gabriel.fernandez@st.com>2016-12-13 15:20:18 +0100
committerStephen Boyd <sboyd@codeaurora.org>2016-12-22 01:09:12 +0100
commit844ca23f5b2e9db925aa5fe0daa5d1d887dba84d (patch)
tree959da94d6ee37ca14d0b51e7952e0cb58998b7e5 /drivers/scsi/wd719x.h
parentclk: stm32f4: Add SAI clocks (diff)
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clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board
In the stm32f469 soc, the 48Mhz clock could be derived from pll-q or from pll-sai-p. The SDIO clock could be also derived from 48Mhz or from sys clock. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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