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| author | Sowjanya Komatineni <skomatineni@nvidia.com> | 2019-08-16 21:42:05 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-29 13:30:16 +0100 |
| commit | c7ccfccabb0f819eae1a191ccd94269f577e4523 (patch) | |
| tree | ca090522e910aa1d1b1c5337a54c6c2b65b01bf0 /drivers/soc/tegra/pmc.c | |
| parent | soc/tegra: pmc: Configure core power request polarity (diff) | |
| download | linux-c7ccfccabb0f819eae1a191ccd94269f577e4523.tar.xz linux-c7ccfccabb0f819eae1a191ccd94269f577e4523.zip | |
soc/tegra: pmc: Configure deep sleep control settings
Tegra210 and prior Tegra chips have deep sleep entry and wakeup related
timings which are platform specific that should be configured before
entering into deep sleep.
Below are the timing specific configurations for deep sleep entry and
wakeup.
- Core rail power-on stabilization timer
- OSC clock stabilization timer after SOC rail power is stabilized.
- Core power off time is the minimum wake delay to keep the system
in deep sleep state irrespective of any quick wake event.
These values depends on the discharge time of regulators and turn OFF
time of the PMIC to allow the complete system to finish entering into
deep sleep state.
These values vary based on the platform design and are specified
through the device tree.
This patch has implementation to configure these timings which are must
to have for proper deep sleep and wakeup operations.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/soc/tegra/pmc.c')
| -rw-r--r-- | drivers/soc/tegra/pmc.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 41e974cd91fe..c9b1baae5d8a 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -88,6 +88,8 @@ #define PMC_CPUPWRGOOD_TIMER 0xc8 #define PMC_CPUPWROFF_TIMER 0xcc +#define PMC_COREPWRGOOD_TIMER 0x3c +#define PMC_COREPWROFF_TIMER 0xe0 #define PMC_PWR_DET_VALUE 0xe4 @@ -2303,7 +2305,7 @@ static const struct tegra_pmc_regs tegra20_pmc_regs = { static void tegra20_pmc_init(struct tegra_pmc *pmc) { - u32 value; + u32 value, osc, pmu, off; /* Always enable CPU power request */ value = tegra_pmc_readl(pmc, PMC_CNTRL); @@ -2329,6 +2331,16 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc) value = tegra_pmc_readl(pmc, PMC_CNTRL); value |= PMC_CNTRL_SYSCLK_OE; tegra_pmc_writel(pmc, value, PMC_CNTRL); + + /* program core timings which are applicable only for suspend state */ + if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { + osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); + pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); + off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); + tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), + PMC_COREPWRGOOD_TIMER); + tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); + } } static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, |