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| author | Enric Balletbo i Serra <enric.balletbo@collabora.com> | 2021-06-25 08:24:48 +0200 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2021-08-06 16:43:23 +0200 |
| commit | 25423731956b3d72bc35d336227c88ada49148e8 (patch) | |
| tree | cb7281597bc789c1e5522b7aadd79db4313f6e2d /drivers/soc | |
| parent | soc: mediatek: mmsys: add MT8365 support (diff) | |
| download | linux-25423731956b3d72bc35d336227c88ada49148e8.tar.xz linux-25423731956b3d72bc35d336227c88ada49148e8.zip | |
soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing
The UFOE (data compression engine) component needs to be enabled to have
the imgtec gpu driver working. If we don't enable it we see a black screen.
Looks like when we switched to use and array for setting the routing
registers in commit 440147639ac7 ("soc: mediatek: mmsys: Use an array for
setting the routing registers") we missed to add this component in the new
routing table, it was present before that commit, so fix it by adding
this component in the mt8173 routing table.
Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers")
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Eizan Miyamoto <eizan@chromium.org>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20210625062448.3462177-1-enric.balletbo@collabora.com
[mb: taking into account mask value]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'drivers/soc')
| -rw-r--r-- | drivers/soc/mediatek/mtk-mmsys.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 5f3e2bf0c40b..9e2b81bd38db 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -262,6 +262,10 @@ static const struct mtk_mmsys_routes mmsys_default_routing_table[] = { DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3, DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK, DSI3_SEL_IN_RDMA2 + }, { + DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0, + DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0, + UFOE_MOUT_EN_DSI0 } }; |