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author | Linus Torvalds <torvalds@linux-foundation.org> | 2021-09-02 00:19:43 +0200 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2021-09-02 00:19:43 +0200 |
commit | 634135a07b887a8ad8904da8c147407650747a38 (patch) | |
tree | 25483fe4cfa60ab4ee144742204680207fe90e93 /drivers/soc | |
parent | Merge tag 'asm-generic-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git... (diff) | |
parent | soc: aspeed-lpc-ctrl: Fix clock cleanup in error path (diff) | |
download | linux-634135a07b887a8ad8904da8c147407650747a38.tar.xz linux-634135a07b887a8ad8904da8c147407650747a38.zip |
Merge tag 'soc-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC updates from Arnd Bergmann:
"There are three noteworthy updates for 32-bit arm platforms this time:
- The Microchip SAMA7 family based on Cortex-A7 gets introduced, a
new cousin to the older SAM9 (ARM9xx based) and SAMA5 (Cortex-A5
based) SoCs.
- The ixp4xx platform (based on Intel XScale) is finally converted to
device tree, and all the old board files are getting removed now.
- The Cirrus Logic EP93xx platform loses support for the old
MaverickCrunch FPU. Support for compiling user space applications
was already removed in gcc-4.9, and the kernel support for old
applications could not be built with clang ias. After confirming
that there are no remaining users, removing this from the kernel
seemed better than adding support for unused features to clang.
There are minor updates to the aspeed, omap and samsung platforms"
* tag 'soc-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (48 commits)
soc: aspeed-lpc-ctrl: Fix clock cleanup in error path
ARM: s3c: delete unneed local variable "delay"
soc: aspeed: Re-enable FWH2AHB on AST2600
soc: aspeed: socinfo: Add AST2625 variant
soc: aspeed: p2a-ctrl: Fix boundary check for mmap
soc: aspeed: lpc-ctrl: Fix boundary check for mmap
ARM: ixp4xx: Delete the Freecom FSG-3 boardfiles
ARM: ixp4xx: Delete GTWX5715 board files
ARM: ixp4xx: Delete Coyote and IXDPG425 boardfiles
ARM: ixp4xx: Delete Intel reference design boardfiles
ARM: ixp4xx: Delete Avila boardfiles
ARM: ixp4xx: Delete the Arcom Vulcan boardfiles
ARM: ixp4xx: Delete Gateway WG302v2 boardfiles
ARM: ixp4xx: Delete Omicron boardfiles
ARM: ixp4xx: Delete the D-Link DSM-G600 boardfiles
ARM: ixp4xx: Delete NAS100D boardfiles
ARM: ixp4xx: Delete NSLU2 boardfiles
arm: omap2: Drop the unused OMAP_PACKAGE_* KConfig entries
arm: omap2: Drop obsolete MACH_OMAP3_PANDORA entry
ARM: ep93xx: remove MaverickCrunch support
...
Diffstat (limited to 'drivers/soc')
-rw-r--r-- | drivers/soc/aspeed/aspeed-lpc-ctrl.c | 35 | ||||
-rw-r--r-- | drivers/soc/aspeed/aspeed-p2a-ctrl.c | 2 | ||||
-rw-r--r-- | drivers/soc/aspeed/aspeed-socinfo.c | 1 |
3 files changed, 28 insertions, 10 deletions
diff --git a/drivers/soc/aspeed/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c index c557ffd0992c..72771e018c42 100644 --- a/drivers/soc/aspeed/aspeed-lpc-ctrl.c +++ b/drivers/soc/aspeed/aspeed-lpc-ctrl.c @@ -37,6 +37,7 @@ struct aspeed_lpc_ctrl { u32 pnor_size; u32 pnor_base; bool fwh2ahb; + struct regmap *scu; }; static struct aspeed_lpc_ctrl *file_aspeed_lpc_ctrl(struct file *file) @@ -51,7 +52,7 @@ static int aspeed_lpc_ctrl_mmap(struct file *file, struct vm_area_struct *vma) unsigned long vsize = vma->vm_end - vma->vm_start; pgprot_t prot = vma->vm_page_prot; - if (vma->vm_pgoff + vsize > lpc_ctrl->mem_base + lpc_ctrl->mem_size) + if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT) return -EINVAL; /* ast2400/2500 AHB accesses are not cache coherent */ @@ -183,13 +184,22 @@ static long aspeed_lpc_ctrl_ioctl(struct file *file, unsigned int cmd, /* * Switch to FWH2AHB mode, AST2600 only. - * - * The other bits in this register are interrupt status bits - * that are cleared by writing 1. As we don't want to clear - * them, set only the bit of interest. */ - if (lpc_ctrl->fwh2ahb) + if (lpc_ctrl->fwh2ahb) { + /* + * Enable FWH2AHB in SCU debug control register 2. This + * does not turn it on, but makes it available for it + * to be configured in HICR6. + */ + regmap_update_bits(lpc_ctrl->scu, 0x0D8, BIT(2), 0); + + /* + * The other bits in this register are interrupt status bits + * that are cleared by writing 1. As we don't want to clear + * them, set only the bit of interest. + */ regmap_write(lpc_ctrl->regmap, HICR6, SW_FWH2AHB); + } /* * Enable LPC FHW cycles. This is required for the host to @@ -285,6 +295,16 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev) return -ENODEV; } + if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-lpc-ctrl")) { + lpc_ctrl->fwh2ahb = true; + + lpc_ctrl->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2600-scu"); + if (IS_ERR(lpc_ctrl->scu)) { + dev_err(dev, "couldn't find scu\n"); + return PTR_ERR(lpc_ctrl->scu); + } + } + lpc_ctrl->clk = devm_clk_get(dev, NULL); if (IS_ERR(lpc_ctrl->clk)) { dev_err(dev, "couldn't get clock\n"); @@ -296,9 +316,6 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev) return rc; } - if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-lpc-ctrl")) - lpc_ctrl->fwh2ahb = true; - lpc_ctrl->miscdev.minor = MISC_DYNAMIC_MINOR; lpc_ctrl->miscdev.name = DEVICE_NAME; lpc_ctrl->miscdev.fops = &aspeed_lpc_ctrl_fops; diff --git a/drivers/soc/aspeed/aspeed-p2a-ctrl.c b/drivers/soc/aspeed/aspeed-p2a-ctrl.c index b60fbeaffcbd..20b5fb2a207c 100644 --- a/drivers/soc/aspeed/aspeed-p2a-ctrl.c +++ b/drivers/soc/aspeed/aspeed-p2a-ctrl.c @@ -110,7 +110,7 @@ static int aspeed_p2a_mmap(struct file *file, struct vm_area_struct *vma) vsize = vma->vm_end - vma->vm_start; prot = vma->vm_page_prot; - if (vma->vm_pgoff + vsize > ctrl->mem_base + ctrl->mem_size) + if (vma->vm_pgoff + vma_pages(vma) > ctrl->mem_size >> PAGE_SHIFT) return -EINVAL; /* ast2400/2500 AHB accesses are not cache coherent */ diff --git a/drivers/soc/aspeed/aspeed-socinfo.c b/drivers/soc/aspeed/aspeed-socinfo.c index e3215f826d17..1ca140356a08 100644 --- a/drivers/soc/aspeed/aspeed-socinfo.c +++ b/drivers/soc/aspeed/aspeed-socinfo.c @@ -26,6 +26,7 @@ static struct { { "AST2600", 0x05000303 }, { "AST2620", 0x05010203 }, { "AST2605", 0x05030103 }, + { "AST2625", 0x05030403 }, }; static const char *siliconid_to_name(u32 siliconid) |