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| author | Yash Shah <yash.shah@sifive.com> | 2020-02-20 06:15:19 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-05-21 00:05:10 +0200 |
| commit | 4a3a37331248d85df9e05e9b1d8210dc5ec81f4e (patch) | |
| tree | e69c611a64e0c6652aa0744119b2efd84e1baeb0 /drivers/soc | |
| parent | riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure (diff) | |
| download | linux-4a3a37331248d85df9e05e9b1d8210dc5ec81f4e.tar.xz linux-4a3a37331248d85df9e05e9b1d8210dc5ec81f4e.zip | |
riscv: Add support to determine no. of L2 cache way enabled
In order to determine the number of L2 cache ways enabled at runtime,
implement a private attribute ("number_of_ways_enabled"). Reading this
attribute returns the number of enabled L2 cache ways at runtime.
Using riscv_set_cacheinfo_ops() hook a custom function, that returns
this private attribute, to the generic ops structure which is used by
cache_get_priv_group() in cacheinfo framework.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'drivers/soc')
| -rw-r--r-- | drivers/soc/sifive/sifive_l2_cache.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c index a5069394cd61..d5f266551880 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_l2_cache.c @@ -9,6 +9,8 @@ #include <linux/interrupt.h> #include <linux/of_irq.h> #include <linux/of_address.h> +#include <linux/device.h> +#include <asm/cacheinfo.h> #include <soc/sifive/sifive_l2_cache.h> #define SIFIVE_L2_DIRECCFIX_LOW 0x100 @@ -31,6 +33,7 @@ static void __iomem *l2_base; static int g_irq[SIFIVE_L2_MAX_ECCINTR]; +static struct riscv_cacheinfo_ops l2_cache_ops; enum { DIR_CORR = 0, @@ -107,6 +110,38 @@ int unregister_sifive_l2_error_notifier(struct notifier_block *nb) } EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); +static int l2_largest_wayenabled(void) +{ + return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF; +} + +static ssize_t number_of_ways_enabled_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%u\n", l2_largest_wayenabled()); +} + +static DEVICE_ATTR_RO(number_of_ways_enabled); + +static struct attribute *priv_attrs[] = { + &dev_attr_number_of_ways_enabled.attr, + NULL, +}; + +static const struct attribute_group priv_attr_group = { + .attrs = priv_attrs, +}; + +const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf) +{ + /* We want to use private group for L2 cache only */ + if (this_leaf->level == 2) + return &priv_attr_group; + else + return NULL; +} + static irqreturn_t l2_int_handler(int irq, void *device) { unsigned int add_h, add_l; @@ -170,6 +205,9 @@ static int __init sifive_l2_init(void) l2_config_read(); + l2_cache_ops.get_priv_group = l2_get_priv_group; + riscv_set_cacheinfo_ops(&l2_cache_ops); + #ifdef CONFIG_DEBUG_FS setup_sifive_debug(); #endif |