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authorAmit Kumar Mahapatra via Alsa-devel <alsa-devel@alsa-project.org>2023-03-10 18:32:03 +0100
committerMark Brown <broonie@kernel.org>2023-03-11 13:34:01 +0100
commit9e264f3f85a56cc109cc2d6010a48aa89d5c1ff1 (patch)
treef4625d50e5c6c4190d20daa8cb770f84f51d540b /drivers/spi/spi-atmel.c
parentspi: mpc5xxx-psc: Remove goto to the unexisted label (diff)
downloadlinux-9e264f3f85a56cc109cc2d6010a48aa89d5c1ff1.tar.xz
linux-9e264f3f85a56cc109cc2d6010a48aa89d5c1ff1.zip
spi: Replace all spi->chip_select and spi->cs_gpiod references with function call
Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod members of struct spi_device to be an array. But changing the type of these members to array would break the spi driver functionality. To make the transition smoother introduced four new APIs to get/set the spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and spi->cs_gpiod references with get or set API calls. While adding multi-cs support in further patches the chip_select & cs_gpiod members of the spi_device structure would be converted to arrays & the "idx" parameter of the APIs would be used as array index i.e., spi->chip_select[idx] & spi->cs_gpiod[idx] respectively. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Acked-by: Heiko Stuebner <heiko@sntech.de> # Rockchip drivers Reviewed-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> # Aspeed driver Reviewed-by: Dhruva Gole <d-gole@ti.com> # SPI Cadence QSPI Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> # spi-stm32-qspi Acked-by: William Zhang <william.zhang@broadcom.com> # bcm63xx-hsspi driver Reviewed-by: Serge Semin <fancer.lancer@gmail.com> # DW SSI part Link: https://lore.kernel.org/r/167847070432.26.15076794204368669839@mailman-core.alsa-project.org Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-atmel.c')
-rw-r--r--drivers/spi/spi-atmel.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 73f80c8ac2ff..7f06305e16cb 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -327,10 +327,10 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
int chip_select;
u32 mr;
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
chip_select = as->native_cs_for_gpio;
else
- chip_select = spi->chip_select;
+ chip_select = spi_get_chipselect(spi, 0);
if (atmel_spi_is_v2(as)) {
spi_writel(as, CSR0 + 4 * chip_select, asd->csr);
@@ -378,10 +378,10 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
int chip_select;
u32 mr;
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
chip_select = as->native_cs_for_gpio;
else
- chip_select = spi->chip_select;
+ chip_select = spi_get_chipselect(spi, 0);
/* only deactivate *this* device; sometimes transfers to
* another device may be active when this routine is called.
@@ -394,7 +394,7 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr);
- if (!spi->cs_gpiod)
+ if (!spi_get_csgpiod(spi, 0))
spi_writel(as, CR, SPI_BIT(LASTXFER));
}
@@ -800,10 +800,10 @@ static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
unsigned long bus_hz;
int chip_select;
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
chip_select = as->native_cs_for_gpio;
else
- chip_select = spi->chip_select;
+ chip_select = spi_get_chipselect(spi, 0);
/* v1 chips start out at half the peripheral bus speed. */
bus_hz = as->spi_clk;
@@ -1189,7 +1189,7 @@ static int atmel_spi_setup(struct spi_device *spi)
as = spi_controller_get_devdata(spi->controller);
/* see notes above re chipselect */
- if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) {
+ if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH)) {
dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
return -EINVAL;
}
@@ -1201,16 +1201,16 @@ static int atmel_spi_setup(struct spi_device *spi)
*/
initialize_native_cs_for_gpio(as);
- if (spi->cs_gpiod && as->native_cs_free) {
+ if (spi_get_csgpiod(spi, 0) && as->native_cs_free) {
dev_err(&spi->dev,
"No native CS available to support this GPIO CS\n");
return -EBUSY;
}
- if (spi->cs_gpiod)
+ if (spi_get_csgpiod(spi, 0))
chip_select = as->native_cs_for_gpio;
else
- chip_select = spi->chip_select;
+ chip_select = spi_get_chipselect(spi, 0);
csr = SPI_BF(BITS, bits - 8);
if (spi->mode & SPI_CPOL)
@@ -1218,7 +1218,7 @@ static int atmel_spi_setup(struct spi_device *spi)
if (!(spi->mode & SPI_CPHA))
csr |= SPI_BIT(NCPHA);
- if (!spi->cs_gpiod)
+ if (!spi_get_csgpiod(spi, 0))
csr |= SPI_BIT(CSAAT);
csr |= SPI_BF(DLYBS, 0);
@@ -1244,7 +1244,7 @@ static int atmel_spi_setup(struct spi_device *spi)
dev_dbg(&spi->dev,
"setup: bpw %u mode 0x%x -> csr%d %08x\n",
- bits, spi->mode, spi->chip_select, csr);
+ bits, spi->mode, spi_get_chipselect(spi, 0), csr);
if (!atmel_spi_is_v2(as))
spi_writel(as, CSR0 + 4 * chip_select, csr);