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| author | Serge Semin <Sergey.Semin@baikalelectronics.ru> | 2020-05-29 15:11:50 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-05-29 16:55:42 +0200 |
| commit | de4c2875a5ff2c886df60f2086c6affca83f890a (patch) | |
| tree | b579db09868ce0b958a2ab88e5a38a7958a6a2ff /drivers/spi/spi-dw.c | |
| parent | Merge series "add ecspi ERR009165 for i.mx6/7 soc family" from Robin Gong <yi... (diff) | |
| download | linux-de4c2875a5ff2c886df60f2086c6affca83f890a.tar.xz linux-de4c2875a5ff2c886df60f2086c6affca83f890a.zip | |
spi: dw: Set xfer effective_speed_hz
Seeing DW APB SSI controller doesn't support setting the exactly
requested SPI bus frequency, but only a rounded frequency determined
by means of the odd-numbered half-worded reference clock divider,
it would be good to tune the SPI core up and initialize the current
transfer effective_speed_hz. By doing so the core will be able to
execute the xfer-related delays with better accuracy.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Feng Tang <feng.tang@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Link: https://lore.kernel.org/r/20200529131205.31838-2-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-dw.c')
| -rw-r--r-- | drivers/spi/spi-dw.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 1edb8cdd11ee..e6fc0bcf214d 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -352,6 +352,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, spi_set_clk(dws, chip->clk_div); } + transfer->effective_speed_hz = dws->max_freq / chip->clk_div; dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); cr0 = dws->update_cr0(master, spi, transfer); |