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authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2024-05-23 12:33:25 +0200
committerMark Brown <broonie@kernel.org>2024-05-23 13:35:09 +0200
commita827ad9b3c2fc243e058595533f91ce41a312527 (patch)
tree5917413d4ba67ab6b3912e03570b72a6eac25d95 /drivers/spi/spi-fsl-spi.c
parentspi: microchip-core-qspi: fix setting spi bus clock rate (diff)
downloadlinux-a827ad9b3c2fc243e058595533f91ce41a312527.tar.xz
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spi: stm32: Revert change that enabled controller before asserting CS
On stm32mp157 enabling the controller before asserting CS makes the hardware trigger spurious interrupts in a tight loop and the transfers fail. Revert the commit that swapped the order of enable and CS. This reintroduces the problem that swapping was supposed to fix, which however is less grave. Reported-by: Leonard Göhrs <l.goehrs@pengutronix.de> Link: https://lore.kernel.org/all/39033ed7-3e57-4339-80b4-fc8919e26aa7@pengutronix.de/ Fixes: 52b62e7a5d4f ("spi: stm32: enable controller before asserting CS") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://msgid.link/r/20240523103326.792907-2-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-fsl-spi.c')
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