diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-08-19 14:58:59 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-08-20 23:38:12 +0200 |
| commit | 8dd71698607f822c3675c366a8a79bc82f7621f8 (patch) | |
| tree | 87599015c96bb9faea3612dca074e8db0d7cf8b0 /drivers/spi/spi-rspi.c | |
| parent | spi: rspi: Remove useless .set_config_register() check (diff) | |
| download | linux-8dd71698607f822c3675c366a8a79bc82f7621f8.tar.xz linux-8dd71698607f822c3675c366a8a79bc82f7621f8.zip | |
spi: rspi: Clean up Bit Rate Division Setting handling
Add a macro for configuring the Bit Rate Division Setting field in
Command Registers, instead of open-coding the same operation using a
hardcoded shift.
Rename "div" to "brdv", as it is not a plain divider value, but controls
a power-of-two divider.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200819125904.20938-3-geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-rspi.c')
| -rw-r--r-- | drivers/spi/spi-rspi.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index 1b635d6b7881..450a42ec2141 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -161,6 +161,7 @@ #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ #define SPCMD_SSLA(i) ((i) << 4) /* SSL Assert Signal Setting */ #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ +#define SPCMD_BRDV(brdv) ((brdv) << 2) #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ @@ -290,24 +291,24 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size) static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) { int spbr; - int div = 0; + int brdv = 0; unsigned long clksrc; /* Sets output mode, MOSI signal, and (optionally) loopback */ rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); clksrc = clk_get_rate(rspi->clk); - while (div < 3) { + while (brdv < 3) { if (rspi->speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */ break; - div++; + brdv++; clksrc /= 2; } /* Sets transfer bit rate */ spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1; rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); - rspi->spcmd |= div << 2; + rspi->spcmd |= SPCMD_BRDV(brdv); /* Disable dummy transmission, set byte access */ rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); |