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| author | Yong Wu <yong.wu@mediatek.com> | 2017-08-21 13:00:16 +0200 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2017-08-22 16:37:58 +0200 |
| commit | e6dec92308628cff5f1f8bd1bcdf87581c9dc676 (patch) | |
| tree | d17007990ff95de3df378b2d6625f25e8b815b54 /drivers/spi/spi-xtensa-xtfpga.c | |
| parent | iommu/mediatek: Move MTK_M4U_TO_LARB/PORT into mtk_iommu.c (diff) | |
| download | linux-e6dec92308628cff5f1f8bd1bcdf87581c9dc676.tar.xz linux-e6dec92308628cff5f1f8bd1bcdf87581c9dc676.zip | |
iommu/mediatek: Add mt2712 IOMMU support
The M4U IP blocks in mt2712 is MTK's generation2 M4U which use the
ARM Short-descriptor like mt8173, and most of the HW registers are
the same.
The difference is that there are 2 M4U HWs in mt2712 while there's
only one in mt8173. The purpose of 2 M4U HWs is for balance the
bandwidth.
Normally if there are 2 M4U HWs, there should be 2 iommu domains,
each M4U has a iommu domain.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/spi/spi-xtensa-xtfpga.c')
0 files changed, 0 insertions, 0 deletions