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authorPaulo Zaneti <paulo.zaneti@datacom.ind.br>2016-10-29 11:02:19 +0200
committerMark Brown <broonie@kernel.org>2016-10-29 20:00:19 +0200
commit73aaf15849d9421fa696c3d7785952d8100042b2 (patch)
treecf4d715eaa01cb504afb6afe5bf0d20e0070bfad /drivers/spi
parentspi: fsl-espi: small fix to error path in fsl_espi_irq (diff)
downloadlinux-73aaf15849d9421fa696c3d7785952d8100042b2.tar.xz
linux-73aaf15849d9421fa696c3d7785952d8100042b2.zip
spi: fsl-espi: fix support for all available clock rates
According to NXP ESPI datasheet, the SPI clock rate is: spi_clk = System_Clock / ( 2 * DIV16 * ( 1 + PM ) ) Where System_Clock is the platform clock divided by 2, DIV16 may be 1 or 16, and PM is a 4 bits integer (0 to 15). Isolating PM on the expression, we get: PM = (System_Clock / ( 2 * DIV16 * spi_clk ) ) - 1 Where System_Clock = mpc8xxx_spi->spibrg / 2, spi_clk = hz, and DIV16 = 1 or DIV16 = 16. So, PM = (mpc8xxx_spi->spibrg / ( 4 * hz) ) - 1 or PM = (mpc8xxx_spi->spibrg / ( 16 * 4 * hz) ) - 1 Current spi-fsl-espi driver can't configure the HW for all supported clock rates. It filters out clock rates for PM = 0 and PM = 1. This patch allows all range of supported clock rates to be configured on the ESPI controller. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-fsl-espi.c28
1 files changed, 12 insertions, 16 deletions
diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
index 1d3c9023391d..8b3a28739d9a 100644
--- a/drivers/spi/spi-fsl-espi.c
+++ b/drivers/spi/spi-fsl-espi.c
@@ -247,8 +247,7 @@ static void fsl_espi_setup_transfer(struct spi_device *spi,
{
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
int bits_per_word = t ? t->bits_per_word : spi->bits_per_word;
- u32 hz = t ? t->speed_hz : spi->max_speed_hz;
- u8 pm;
+ u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz;
struct spi_mpc8xxx_cs *cs = spi->controller_state;
/* mask out bits we are going to set */
@@ -256,22 +255,19 @@ static void fsl_espi_setup_transfer(struct spi_device *spi,
cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
- if ((mpc8xxx_spi->spibrg / hz) > 64) {
+ pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4) - 1;
+
+ if (pm > 15) {
cs->hw_mode |= CSMODE_DIV16;
- pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
-
- WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
- "Will use %d Hz instead.\n", dev_name(&spi->dev),
- hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
- if (pm > 33)
- pm = 33;
- } else {
- pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
+ pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4) - 1;
+
+ WARN_ONCE(pm > 15,
+ "%s: Requested speed is too low: %u Hz. Will use %u Hz instead.\n",
+ dev_name(&spi->dev), hz,
+ mpc8xxx_spi->spibrg / (4 * 16 * (15 + 1)));
+ if (pm > 15)
+ pm = 15;
}
- if (pm)
- pm--;
- if (pm < 2)
- pm = 2;
cs->hw_mode |= CSMODE_PM(pm);